SGLS380I September   2008  – May 2024 TL720M05-Q1

PRODMIX  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Typical Characteristics
  7. 6 Parameter Measurement Information
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagrams
    3. 7.3 Feature Description
      1. 7.3.1 Undervoltage Lockout
      2. 7.3.2 Thermal Shutdown
      3. 7.3.3 Current Limit
    4. 7.4 Device Functional Modes
      1. 7.4.1 Normal Operation
      2. 7.4.2 Dropout Operation
      3. 7.4.3 Disabled
  9. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Input and Output Capacitor Selection
        1. 8.1.1.1 Legacy Chip Capacitor Selection
        2. 8.1.1.2 New Chip Output Capacitor
        3. 8.1.1.3 New Chip Input Capacitor
      2. 8.1.2 Dropout Voltage
      3. 8.1.3 Reverse Current
      4. 8.1.4 Power Dissipation (PD)
        1. 8.1.4.1 Thermal Performance Versus Copper Area
        2. 8.1.4.2 Power Dissipation Versus Ambient Temperature
      5. 8.1.5 Estimating Junction Temperature
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Input Capacitor
        2. 8.2.2.2 Output Capacitor
      3. 8.2.3 Application Curves
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Examples
  10. 9 Device and Documentation Support
    1. 9.1 Device Support
      1. 9.1.1 Evaluation Module
      2. 9.1.2 Device Nomenclature
      3. 9.1.3 Development Support
    2. 9.2 Documentation Support
      1. 9.2.1 Related Documentation
    3. 9.3 Receiving Notification of Documentation Updates
    4. 9.4 Support Resources
    5. 9.5 Trademarks
    6. 9.6 Electrostatic Discharge Caution
    7. 9.7 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • KVU|3
  • PWP|20
  • KTT|3
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5.5 Electrical Characteristics

specified at TJ = –40°C to +150°C, VIN = 13.5V,  IOUT = 0mA, COUT = 2.2µF, 1mΩ < COUT ESR < 2Ω, and  CIN = 1µF (unless otherwise noted); typical values are at TJ = 25°C.
PARAMETER Test Conditions MIN TYP MAX UNIT
VOUT Regulated output (for legacy chip) VIN = 6V to 28V, IOUT = 5mA to 400mA 4.9 5.0 5.1 V
VIN = 6V to 40V, IOUT = 5mA to 400mA 4.9 5.0 5.1
Regulated output (for new chip) VIN = VOUT + 1V to 40V, IOUT = 100µA to 450mA, TJ = 25ºC(1) –0.85 0.85 %
VIN = VOUT + 1V to 40V, IOUT = 100µA to 500mA, TJ = 25ºC(1) –0.85 0.85
VIN = VOUT + 1V to 40V, IOUT = 100µA to 450mA(1) –1.15 1.15
VIN = VOUT + 1V to 40V, IOUT = 100µA to 500mA(1) –1.15 1.15
ΔVOUT(ΔIOUT) Load regulation (for legacy chip) IOUT = 5mA to 400mA 15 30 mV
Load regulation (for new chip) VIN = VOUT + 1V, IOUT = 100µA to 450mA 0.425 %
ΔVOUT(ΔVIN) Line regulation (for legacy chip) VIN = 8V to 32V,  IOUT = 5mA –15 5 15 mV
Line regulation (for new chip) VIN = VOUT + 1V to 40V,  IOUT = 100µA 0.2 %
ΔVOUT Load transient response settling time (for new chip)(2) tR = tF = 1µs; COUT = 10µF 100 µs
ΔVOUT Load transient response overshoot, undershoot (for new chip)(2) tR = tF = 1µs; COUT = 10µF IOUT = 150mA to 350mA –2% %VOUT
IOUT = 350mA to 150mA 10%
IOUT = 0mA to 500mA –10%
IQ Quiescent current (for legacy chip)
IQ = IIN – IOUT		 IOUT = 1mA TJ = 25ºC 100 220 µA
TJ ≤ 85ºC 100 220
IOUT = 250mA 5 10 mA
IOUT = 400mA 12 22
Quiescent current (for new chip) VIN = VOUT + 1V to 40V, IOUT = 0mA, TJ = 25ºC(3) 17 21 µA
VIN = VOUT + 1V to 40V, IOUT = 0mA(3) 26
IOUT = 500µA 35
VDO Dropout voltage (for legacy chip) IOUT = 300mA 250 500 mV
Dropout voltage (for new chip) IOUT ≤ 1mA, VIN = VOUT(NOM) x 0.95 46
IOUT = 315mA, VIN = VOUT(NOM) 275 400
IOUT = 450mA, VIN = VOUT(NOM) 360 525
IOUT = 500mA, VIN = VOUT(NOM) 390 575
VUVLO(RISING) Rising input supply UVLO (for new chip) VIN rising 2.6 2.7 2.82 V
VUVLO(FALLING) Falling input supply UVLO (for new chip) VIN falling 2.38 2.5 2.6 V
VUVLO(HYST) V UVLO(IN) hysteresis (for new chip) 230 mV
ICL Output current limit (for legcacy chip) VIN = VOUT + 1V, VOUT short to 90% x VOUT(NOM) 450 700 950 mA
Output current limit (for new chip) VIN = VOUT + 1V, VOUT short to 90% x VOUT(NOM) 540 780
PSRR Power-supply rejection ratio (for legacy chip) VIN - VOUT = 1V, frequency = 100Hz, Vr = 0.5Vpp, IOUT = 450mA 60 dB
Power-supply rejection ratio (for new chip) VIN - VOUT = 1V, frequency = 1kHz, IOUT = 450mA 70
TJ Junction temperature –40 150 °C
TSD(SHUTDOWN) Junction shutdown temperature (for new chip) 175
TSD(HYST) Hysteresis of thermal shutdown (for new chip) 20
ΔVOUT/ΔT Temperature output voltage drift (for legacy chip) 0.5 mV/K
(1) Power dissipation is limited to 2W for device production testing purposes. The power dissipation is potentially higher during normal operation. See the Thermal Performance section for more information on how much power the device can dissipate while maintaining a junction temperature below 150℃.
(2) Specified by design.
(3) For the adjustable output this is tested in unity gain and resistor current is not included.