SLOS467H October   2006  – January 2015 TL971 , TL972 , TL974

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Simplified Schematic
  5. 5 Revision History
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Slew Rate
      2. 8.3.2 Unity-Gain Bandwidth
      3. 8.3.3 Low Total Harmonic Distortion
      4. 8.3.4 Operating Voltage
    4. 8.4 Device Functional Modes
  9. 9 Application and Implementation
    1. 9.1 Typical Application
      1. 9.1.1 Design Requirements
      2. 9.1.2 Detailed Design Procedure
        1. 9.1.2.1 Output Voltage Swing
        2. 9.1.2.2 Supply and Input Voltage
      3. 9.1.3 Application Curves for Output Characteristics
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Related Links
    2. 12.2 Trademarks
    3. 12.3 Electrostatic Discharge Caution
    4. 12.4 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • D|8
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7 Specifications

7.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)(1)
MIN MAX UNIT
VCC Supply voltage range 2.7 15 V
VID Differential input voltage(2) ±1 V V
VIN Input voltage range(3) VCC– – 0.3 VCC+ + 0.3 V
TJ Maximum junction temperature 150 °C
Tstg Storage temperature range –65 150 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditionsis not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) Differential voltages for the noninverting input terminal are with respect to the inverting input terminal.
(3) The input and output voltages must never exceed VCC + 0.3 V.

7.2 ESD Ratings

VALUE UNIT
V(ESD) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins(1) 2000 V
Charged device model (CDM), per JEDEC specification JESD22-C101, all pins(2) 1500
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

7.3 Recommended Operating Conditions

MIN MAX UNIT
VCC Supply voltage 2.7 12 V
VICM Common-mode input voltage VCC– + 1.15 VCC+ – 1.15 V
TA Operating free-air temperature –40 125 °C

7.4 Thermal Information

THERMAL METRIC(1) TL971 TL972 TL974 UNIT
D(2) DBV(2) D(2) DGK(3) DRG(3) P(2) PW(2) D(2) N(2) PW(2)
8 PINS 5 PINS 8 PINS 14 PINS
RθJA Package thermal impedance, junction to free air 97 206 97 172 44 85 149 86 80 113 °C/W
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report (SPRA953).
(2) Package thermal impedance is calculated in accordance with JESD 51-7.
(3) Package thermal impedance is calculated in accordance with JESD 51-5.

7.5 Electrical Characteristics

VCC+ = 2.5 V, VCC– = –2.5 V, full-range TA = –40°C to 125°C (unless otherwise noted)
PARAMETER TEST CONDITIONS TA MIN TYP MAX UNIT
VIO Input offset voltage 25°C 1 4 mV
Full range 6
αVIO Input offset voltage drift VICM = 0 V, VO = 0 V 25°C 5 μV/°C
IIO Input offset current VICM = 0 V, VO = 0 V 25°C 10 150 nA
IIB Input bias current VICM = 0 V, VO = 0 V 25°C 200 750 nA
Full range 1000
VICM Common-mode input voltage 25°C –1.35 1.35 V
CMRR Common-mode rejection ratio VICM = ±1.35 V 25°C 60 85 dB
SVR Supply-voltage rejection ratio VCC = ±2 V to ±3 V 25°C 60 70 dB
AVD Large-signal voltage gain RL = 2 kΩ 25°C 70 80 dB
VOH High-level output voltage RL = 2 kΩ 25°C 2 2.4 V
VOL Low-level output voltage RL = 2 kΩ 25°C –2.4 –2 V
Isource Output source current 25°C 1.2 1.4 mA
VOUT = ±2.5 V Full range 1
Isink Output sink current 25°C 50 80 mA
VOUT = ±2.5 V Full range 25
ICC Supply current (per amplifier) Unity gain, No load 25°C 2 2.8 mA
Full range 3.2
GBWP Gain bandwidth product f = 100 kHz, RL = 2 kΩ, CL = 100 pF 25°C 8.5 12 MHz
SR Slew rate AV = 1, VIN = ±1 V 25°C 2.8 5 V/μs
Full range 2.8
Φm Phase margin at unity gain RL = 2 kΩ, CL =100 pF 25°C 60 °
Gm Gain margin RL = 2 kΩ, CL =100 pF 25°C 10 dB
Vn Equivalent input noise voltage f = 100 kHz 25°C 4 nV/√Hz
THD Total harmonic distortion f = 1 kHz, Av = –1, RL = 10 kΩ 25°C 0.003 %

7.6 Typical Characteristics

g_gain_phase_freq_27v.gifFigure 1. Gain And Phase vs Frequency
thd_freq.gifFigure 3. Total Harmonic Distortion vs Frequency
g_thdn_vout_5v.gifFigure 5. Total Harmonic Distortion + Noise vs Output Voltage
g_gbw_iout.gifFigure 7. Gain Bandwidth Product vs Output Current
g_phase_m_iout.gifFigure 9. Phase Margin vs Output Current
g_gain_margin_vcc.gifFigure 11. Gain Margin vs Supply Voltage
g_psrr_freq.gifFigure 13. Power-Supply Ripple Rejection vs Frequency
g_zout_freq.gifFigure 15. Output Impedance vs Frequency
g_gain_phase_freq_5v.gifFigure 2. Gain And Phase vs Frequency
g_thdn_vout_27v.gifFigure 4. Total Harmonic Distortion + Noise vs Output Voltage
g_vn_freq.gifFigure 6. Input Voltage Noise vs Frequency
g_gbw_vcc.gifFigure 8. Gain Bandwidth Product vs Supply Voltage
g_phase_margin_vcc.gifFigure 10. Phase Margin vs Supply Voltage
g_input_resp.gifFigure 12. Input Response
g_vout_iout.gifFigure 14. Output Voltage vs Output Current
slew_rate_vcc.gifFigure 16. Slew Rate vs Supply Voltage