7.5.2 GENERAL_CFG Register (Address = 0x1) [reset = 0x0]
GENERAL_CFG is shown in Figure 35 and described in Table 10.
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Figure 35. GENERAL_CFG Register
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
RESERVED |
CH_RST |
CAL |
RST |
R-0b |
R/W-0b |
R/W-0b |
W-0b |
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Table 10. GENERAL_CFG Register Field Descriptions
Bit |
Field |
Type |
Reset |
Description |
7-3 |
RESERVED |
R |
0b |
Reserved. Reads return 0b. |
2 |
CH_RST |
R/W |
0b |
Force all channels to be analog inputs.
0b = Normal operation.
1b = All channels are set as analog inputs irrespective of configuration in other registers.
|
1 |
CAL |
R/W |
0b |
Calibrate ADC offset.
0b = Normal operation.
1b = ADC offset is calibrated. After calibration is complete, this bit is set to 0b.
|
0 |
RST |
W |
0b |
Software reset all registers to default values.
0b = Normal operation.
1b = Device is reset. After reset is complete, this bit is set to 0b and BOR bit is set to 1b.
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