SBAS961A
May 2019 – April 2020
TLA2528
PRODUCTION DATA.
1
Features
2
Applications
3
Description
Device Images
TLA2528 Block Diagram and Applications
4
Revision History
5
Pin Configuration and Functions
Pin Functions
6
Specifications
6.1
Absolute Maximum Ratings
6.2
ESD Ratings
6.3
Recommended Operating Conditions
6.4
Thermal Information
6.5
Electrical Characteristics
Table 1.
I2C Timing Requirements
Table 2.
Timing Requirements
Table 3.
I2C Switching Characteristics
6.6
Switching Characteristics
6.7
Typical Characteristics
7
Detailed Description
7.1
Overview
7.2
Functional Block Diagram
7.3
Feature Description
7.3.1
Multiplexer and ADC
7.3.2
Reference
7.3.3
ADC Transfer Function
7.3.4
ADC Offset Calibration
7.3.5
I2C Address Selector
7.3.6
Programmable Averaging Filter
7.3.7
General-Purpose I/Os (GPIOs)
7.3.8
Oscillator and Timing Control
7.3.9
Output Data Format
7.3.10
I2C Protocol Features
7.3.10.1
General Call
7.3.10.2
General Call With Software Reset
7.3.10.3
General Call With a Software Write to the Programmable Part of the Slave Address
7.3.10.4
Configuring the Device for High-Speed I2C Mode
7.4
Device Functional Modes
7.4.1
Device Power-Up and Reset
7.4.2
Manual Mode
7.4.3
Auto-Sequence Mode
7.5
Programming
7.5.1
Reading Registers
7.5.1.1
Single Register Read
7.5.1.2
Reading a Continuous Block of Registers
7.5.2
Writing Registers
7.5.2.1
Single Register Write
7.5.2.2
Set Bit
7.5.2.3
Clear Bit
7.5.2.4
Writing a Continuous Block of Registers
7.6
TLA2528 Registers
7.6.1
SYSTEM_STATUS Register (Address = 0x0) [reset = 0x80]
Table 13.
SYSTEM_STATUS Register Field Descriptions
7.6.2
GENERAL_CFG Register (Address = 0x1) [reset = 0x0]
Table 14.
GENERAL_CFG Register Field Descriptions
7.6.3
DATA_CFG Register (Address = 0x2) [reset = 0x0]
Table 15.
DATA_CFG Register Field Descriptions
7.6.4
OSR_CFG Register (Address = 0x3) [reset = 0x0]
Table 16.
OSR_CFG Register Field Descriptions
7.6.5
OPMODE_CFG Register (Address = 0x4) [reset = 0x0]
Table 17.
OPMODE_CFG Register Field Descriptions
7.6.6
PIN_CFG Register (Address = 0x5) [reset = 0x0]
Table 18.
PIN_CFG Register Field Descriptions
7.6.7
GPIO_CFG Register (Address = 0x7) [reset = 0x0]
Table 19.
GPIO_CFG Register Field Descriptions
7.6.8
GPO_DRIVE_CFG Register (Address = 0x9) [reset = 0x0]
Table 20.
GPO_DRIVE_CFG Register Field Descriptions
7.6.9
GPO_VALUE Register (Address = 0xB) [reset = 0x0]
Table 21.
GPO_VALUE Register Field Descriptions
7.6.10
GPI_VALUE Register (Address = 0xD) [reset = 0x0]
Table 22.
GPI_VALUE Register Field Descriptions
7.6.11
SEQUENCE_CFG Register (Address = 0x10) [reset = 0x0]
Table 23.
SEQUENCE_CFG Register Field Descriptions
7.6.12
CHANNEL_SEL Register (Address = 0x11) [reset = 0x0]
Table 24.
CHANNEL_SEL Register Field Descriptions
7.6.13
AUTO_SEQ_CH_SEL Register (Address = 0x12) [reset = 0x0]
Table 25.
AUTO_SEQ_CH_SEL Register Field Descriptions
8
Application and Implementation
8.1
Application Information
8.2
Typical Applications
8.2.1
Mixed-Channel Configuration
8.2.1.1
Design Requirements
8.2.1.2
Detailed Design Procedure
8.2.1.2.1
Digital Input
8.2.1.2.2
Digital Open-Drain Output
8.2.1.3
Application Curve
8.2.2
Digital Push-Pull Output
9
Power Supply Recommendations
9.1
AVDD and DVDD Supply Recommendations
10
Layout
10.1
Layout Guidelines
10.2
Layout Example
11
Device and Documentation Support
11.1
Receiving Notification of Documentation Updates
11.2
Community Resources
11.3
Trademarks
11.4
Electrostatic Discharge Caution
11.5
Glossary
12
Mechanical, Packaging, and Orderable Information
Package Options
Mechanical Data (Package|Pins)
RTE|16
MPQF149D
Thermal pad, mechanical data (Package|Pins)
RTE|16
QFND525B
Orderable Information
sbas961a_oa
sbas961a_pm
2
Applications
Mobile robot CPU boards
Rack servers
Intra-DC interconnect (metro)