7.6.4 OSR_CFG Register (Address = 0x3) [reset = 0x0]
OSR_CFG is shown in Figure 36 and described in Table 16.
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Figure 36. OSR_CFG Register
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
RESERVED |
OSR[2:0] |
R-0b |
R/W-0b |
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Table 16. OSR_CFG Register Field Descriptions
Bit |
Field |
Type |
Reset |
Description |
7-3 |
RESERVED |
R |
0b |
Reserved. Reads return 0b. |
2-0 |
OSR[2:0] |
R/W |
0b |
Selects the oversampling ratio for ADC conversion result.
0b = OSR = 0.
1b = OSR = 2.
10b = OSR = 4.
11b = OSR = 8.
100b = OSR = 16.
101b = OSR = 32.
110b = OSR = 64.
111b = OSR = 128.
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