7.6.6 PIN_CFG Register (Address = 0x5) [reset = 0x0]
PIN_CFG is shown in Figure 38 and described in Table 18.
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Figure 38. PIN_CFG Register
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
PIN_CFG[7:0] |
R/W-0b |
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Table 18. PIN_CFG Register Field Descriptions
Bit |
Field |
Type |
Reset |
Description |
7-0 |
PIN_CFG[7:0] |
R/W |
0b |
Configure device channels CH7 through CH0 as analog input or GPIO.
0b = Channel is configured as analog input.
1b = Channel is configured as GPIO.
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