SLOS985 June   2017 TLC2274M-MIL

PRODUCTION DATA.  

  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 TLC2274M-MIL Electrical Characteristics VDD = 5 V
    6. 6.6 TLC2274M-MIL Electrical Characteristics VDD± = ±5 V
    7. 6.7 Typical Characteristics
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
    4. 7.4 Device Functional Modes
  8. Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Macromodel Information
    2. 8.2 Typical Application
      1. 8.2.1 High-Side Current Monitor
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
          1. 8.2.1.2.1 Differential Amplifier Equations
        3. 8.2.1.3 Application Curves
  9. Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Receiving Notification of Documentation Updates
    2. 11.2 Community Resources
    3. 11.3 Trademarks
    4. 11.4 Electrostatic Discharge Caution
    5. 11.5 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Pin Configuration and Functions

D, J, or N Package
14-Pin SOIC, CDIP, or PDIP
Top View
FK Package
20-Pin LCCC
Top View
NC – No internal connection
W Package
10-Pin CFP
Top View
NC – No internal connection

Pin Functions

PIN I/O DESCRIPTION
NAME NO.
D, J, N, or W FK
1IN+ 3 4 I Non-inverting input, Channel 1
1IN– 2 3 I Inverting input, Channel 1
1OUT 1 2 O Output, Channel 1
2IN+ 5 8 I Non-inverting input, Channel 2
2IN– 6 9 I Inverting input, Channel 2
2OUT 7 10 O Output, Channel 2
3IN+ 10 14 I Non-inverting input, Channel 3
3IN– 9 13 I Inverting input, Channel 3
3OUT 8 12 O Output, Channel 3
4IN+ 12 18 I Non-inverting input, Channel 4
4IN– 13 19 I Inverting input, Channel 4
4OUT 14 20 O Output, Channel 4
VDD+ 4 6 Positive (highest) supply
VDD 11 16 Negative (lowest) supply
VDD–/GND Negative (lowest) supply
NC 1, 5, 7, 11, 15, 17 No connection