SLFS083A July   2024  – October 2024 TLC3555-Q1

PRODMIX  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Switching Characteristics
    7. 5.7 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Monostable Operation
      2. 6.3.2 Astable Operation
      3. 6.3.3 Power-on Reset
      4. 6.3.4 Thermal Shutdown
    4. 6.4 Device Functional Modes
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Applications
      1. 7.2.1 Missing-Pulse Detector
        1. 7.2.1.1 Design Requirements
        2. 7.2.1.2 Detailed Design Procedure
        3. 7.2.1.3 Application Curve
      2. 7.2.2 Pulse-Width Modulation
        1. 7.2.2.1 Design Requirements
        2. 7.2.2.2 Detailed Design Procedure
        3. 7.2.2.3 Application Curve
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 Documentation Support
      1. 8.1.1 Related Documentation
    2. 8.2 Receiving Notification of Documentation Updates
    3. 8.3 Support Resources
    4. 8.4 Trademarks
    5. 8.5 Electrostatic Discharge Caution
    6. 8.6 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • D|8
  • DDF|8
Thermal pad, mechanical data (Package|Pins)
Orderable Information

3 Description

The TLC3555-Q1 is a monolithic timing circuit fabricated using a TI CMOS process. The timer is fully compatible with CMOS, TTL, and MOS logic and operates at frequencies to 3MHz and even beyond. The TLC3555-Q1 improves upon the existing TLC555-Q1 from both a performance and feature standpoint, with tighter specification tolerances and additional features, such as thermal shutdown and power-on reset.

The trigger, threshold, and reset logic of the TLC3555-Q1 follow the same truth table as the TLC555-Q1. Set the reset pin (RESET) high for typical operation, or set the reset pin low to reset the flip-flop and force the output low. The TLC3555-Q1 features an internal pullup resistor from RESET to VDD, which can reduce passive count and save board area.

As a result of low propagation delay and rapid rise and fall times, the TLC3555-Q1 supports higher-frequency astable operation than previous timers such as the NE555 and TLC555-Q1. At a 15V supply, the TLC3555-Q1 achieves a clean square wave at 3.1MHz in TI's conventional astable test circuit. When used as an oscillator, with the output and inputs tied together, the TLC3555-Q1 achieves an oscillatory frequency of 7.2MHz. Circuit parasitics dominate the response at high frequencies. In addition to the D package, which is pin-to-pin compatible with the TLC555-Q1, the TLC3555-Q1 is offered in a DDF package that enables concise implementations with reduced parasitics.

Package Information
PART NUMBER PACKAGE(1) PACKAGE SIZE(2)
TLC3555-Q1 D (SOIC, 8) 4.9mm × 6.0mm
DDF (SOT-23-THIN, 8)(3) 2.9mm x 2.8mm
(1) For more information, see Section 10.
(2) The package size (length × width) is a nominal value and includes pins, where applicable.
(3) Advance information (not Production Data).