3 Description

The TLC555 is a monolithic timing circuit fabricated using the TI LinCMOS™ technology. The timer is fully compatible with CMOS, TTL, and MOS logic and operates at frequencies up to 2 MHz. Because of a high input impedance, this device supports smaller timing capacitors than those supported by the NE555 or LM555. As a result, more accurate time delays and oscillations are possible. Power consumption is low across the full range of power-supply voltage.

Like the NE555, the TLC555 has a trigger level equal to approximately one-third of the supply voltage and a threshold level equal to approximately two-thirds of the supply voltage. These levels can be altered by use of the control voltage terminal (CONT). When the trigger input (TRIG) falls below the trigger level, the flip-flop is set and the output goes high. If TRIG is above the trigger level and the threshold input (THRES) is above the threshold level, the flip-flop is reset and the output is low. The reset input (RESET) can override all other inputs and can be used to initiate a new timing cycle. If RESET is low, the flip-flop is reset and the output is low. Whenever the output is low, a low-impedance path is provided between the discharge terminal (DISCH) and GND. All unused inputs must be tied to an appropriate logic level to prevent false triggering.

Package Information

PART NUMBER	PACKAGE⁽¹⁾	PACKAGE SIZE⁽²⁾
TLC555C	SOIC (8)	4.9 mm × 6.0 mm
	PDIP (8)	9.81 mm × 9.43 mm
	SOP (8)	6.2 mm × 7.8 mm
	TSSOP (14)	5.0 mm × 6.4 mm
TLC555I	SOIC (8)	4.9 mm × 6.0 mm
TLC555I	PDIP (8)	9.81 mm × 9.43 mm
TLC555M	LCCC (20)	8.89 mm × 8.89 mm
TLC555M	CDIP (8)	9.6 mm × 9.0 mm
TLC555Q	SOIC (8)	4.9 mm × 6.0 mm

(1) For more information, see Section 10.

(2) The package size (length × width) is a nominal value and includes pins, where applicable.

Simplified Schematic