As shown in Figure 6-5, adding a second resistor, R_B, to the circuit of Figure 6-2 and connecting the trigger input to the threshold input causes the timer to self-trigger and run as a multivibrator. The capacitor C charges through R_A and R_B and then discharges through R_B only. Therefore, the duty cycle is controlled by the values of R_A and R_B.

This astable connection results in capacitor C charging and discharging between the threshold-voltage level
(≈ 0.67 × V_CC) and the trigger-voltage level (≈ 0.33 × V_CC). As in the monostable circuit, charge and discharge times (and, therefore, the frequency and duty cycle) are independent of the supply voltage.

Decouple CONT voltage to ground with a capacitor to improve operation. Reevaluate for individual applications.

Figure 6-5 Circuit for Astable Operation

RA = 5 kΩ	RB = 3 kΩ	C = 0.15 µF
See Figure 6-5

Figure 6-6 Typical Astable Waveforms

Figure 6-6 shows typical waveforms generated during astable operation. The output high-level duration t_H and low-level duration t_L for frequencies below 100 kHz can be calculated as follows:

Equation 1.

Equation 2.

Other useful relationships are shown below:

Equation 3.

Equation 4.

Equation 5.

Equation 6.

Equation 7.

Equation 1 to Equation 7 do not account for any propagation delay times from the TRIG and THRES inputs to DISCH output. These delay times add directly to the period and overcharge the capacitor, which creates differences between calculated and actual values that increase with frequency. In addition, the internal on-state resistance r_on during discharge adds to R_B to provide another source of timing error in the calculation when R_B is very low. The following equations provide better agreement with measured values. The formulas in Equation 8 represent the actual low and high times when used at higher frequencies (beyond 100 kHz) because propagation delay and discharge on resistance is added to the formulas. The value of C_T includes both the nominal or deliberate timing capacitance, as well as parasitic capacitance on the PCB. Decoupling capacitance on CONT also affects the duty cycle, with an error contribution that depends on the capacitor leakage resistance. For additional discussion, see the Design low-duty-cycle timer circuits article.

Equation 8.

These equations and those given earlier are similar in that a time constant is multiplied by the logarithm of a number or function. The limit values of the logarithmic terms must be between ln(2) at low frequencies, and ln(3) at extremely high frequencies. For a duty cycle close to 50%, an appropriate constant for the logarithmic terms can be substituted with good results. Output waveform duty cycles less than 50% require that t_c(H) / t_c(L) < 1 and possibly that R_A ≤ r_on. These conditions can be difficult to obtain. Figure 6-8 shows the nominal free-running frequency associated with various combinations of C_T and R_A + 2 × R_B.

Figure 6-7 Trigger and Threshold Voltage Waveform

Figure 6-8 Nominal Free-Running Frequency vs Timing Capacitance
Resistance = R_A + 2 × R_B