8.3.1 Power-On Reset

When power is applied to V_CC, an internal power-on reset holds the TLC59108F in a reset condition until V_CC has reached V_POR. At this point, the reset condition is released and the TLC59108F registers and I²C bus state machine are initialized to their default states causing all the channels to be deselected. Thereafter, V_CC must be lowered below 0.2 V to reset the device.

8.3.2 External Reset

A reset can be accomplished by holding the RESET pin low for a minimum of t_W. The TLC59108F registers and I²C state machine will be held in their default state until the RESET input is once again high.

This input requires a pullup resistor to V_CC if no active connection is used.

8.3.3 Software Reset

The Software Reset Call (SWRST Call) allows all the devices in the I²C bus to be reset to the power-up state value through a specific I²C bus command. To be performed correctly, the I²C bus must be functional and there must be no device hanging the bus.

The SWRST Call function is defined as the following:

1. A Start command is sent by the I²C bus master.
2. The reserved SWRST I²C bus address 1001 011 with the R/W bit set to 0 (write) is sent by the I²C bus master.
3. The TLC59108F device(s) acknowledge(s) after seeing the SWRST Call address 1001 0110 (96h) only. If the R/W bit is set to 1 (read), no acknowledge is returned to the I²C bus master.
4. Once the SWRST Call address has been sent and acknowledged, the master sends two bytes with two specific values (SWRST data byte 1 and byte 2):
   1. Byte1 = A5h: the TLC59108F acknowledges this value only. If byte 1 is not equal to A5h, the TLC59108F does not acknowledge it.
   2. Byte 2 = 5Ah: the TLC59108F acknowledges this value only. If byte 2 is not equal to 5Ah, the TLC59108F does not acknowledge it.

If more than two bytes of data are sent, the TLC59108F does not acknowledge any more.

5. Once the correct two bytes (SWRST data byte 1 and byte 2 only) have been sent and correctly acknowledged, the master sends a Stop command to end the SWRST Call. The TLC59108F then resets to the default value (power-up value) and is ready to be addressed again within the specified bus free time (t_BUF).

The I²C bus master may interpret a non-acknowledge from the TLC59108F (at any time) as a SWRST Call Abort. The TLC59108F does not initiate a reset of its registers. This happens only when the format of the Start Call sequence is not correct.

8.3.4 Individual Brightness Control With Group Dimming or Blinking

A 97-kHz fixed frequency signal with programmable duty cycle (8 bits, 256 steps) is used to control individually the brightness for each LED.

On top of this signal, one of the following signals can be superimposed (this signal can be applied to the 4 LED outputs):

• A lower 190-Hz fixed frequency signal with programmable duty cycle (8 bits, 256 steps) is used to provide a global brightness control.
• A programmable frequency signal from 24 Hz to 1/10.73 s (8 bits, 256 steps) is used to provide a global blinking control.

A. Minimum pulse width for LEDn brightness control is 40 ns.

B. Minimum pulse width for group dimming is 20.48 μs.

C. When M = 1 (GRPPWM register value), the resulting LEDn brightness control and group dimming signal will have two pulses of the LED brightness control signal (pulse width = N × 40 ns,w ith N defined in the PWMx register).

D. The resulting brightness plus group dimming signal shown above demonstrate a resulting control signal with M = 4 (8 pulses).

Figure 7. Brightness + Group Dimming Signals

8.5.1 Device Address

Following a Start condition, the bus master must output the address of the slave it is accessing.

8.5.2 Regular I²C Bus Slave Address

The I²C bus slave address of the TLC59108F is shown in Figure 8. To conserve power, no internal pullup resistors are incorporated on the hardware-selectable address pins, and they must be pulled high or low. For buffer management purpose, a set of sector information data should be stored.

Figure 8. Slave Address

The last bit of the address byte defines the operation to be performed. When set to logic 1, a read operation is selected. When set to logic 0, a write operation is selected.

8.5.3 LED All Call I²C Bus Address

• Default power-up value (ALLCALLADR address register): 90h or 1001 000
• Programmable through I²C bus (volatile programming)
• At power-up, LED All Call I²C bus address is enabled. TLC59108F sends an ACK when 90h (R/W = 0) or 91h (R/W = 1) is sent by the master.

8.5.4 LED Sub Call I²C Bus Address

• Three different I²C bus address can be used
• Default power-up values:
  • SUBADR1 register: 92h or 1001 001
  • SUBADR2 register: 94h or 1001 010
  • SUBADR3 register: 98h or 1001 100
• Programmable through I²C bus (volatile programming)
• At power-up, Sub Call I²C bus address is disabled. TLC59108F does not send an ACK when 92h (R/W = 0) or 93h (R/W = 1) or 94h (R/W = 0) or 95h (R/W = 1) or 98h (R/W = 0) or 99h (R/W = 1) is sent by the master.

8.5.5 Software Reset I²C Bus Address

The address shown in Figure 9 is used when a reset of the TLC59108F needs to be performed by the master. The software reset address (SWRST Call) must be used with R/W = 0. If R/W = 1, the TLC59108F does not acknowledge the SWRST. See Software Reset for more detail.

Figure 9. Software Reset Address

8.5.6 Characteristics of the I²C Bus

The I²C bus is for two-way two-line communication between different devices or modules. The two lines are a serial data line (SDA) and a serial clock line (SCL). Both lines must be connected to a positive supply through a pullup resistor when connected to the output stages of a device. Data transfer may be initiated only when the bus is not busy.

8.5.6.1 Bit Transfer

One data bit is transferred during each clock pulse. The data on the SDA line must remain stable during the high period of the clock pulse as changes in the data line at this time will be interpreted as control signals (see Figure 10).

Figure 10. Bit Transfer

8.5.6.2 Start and Stop Conditions

Both data and clock lines remain high when the bus is not busy. A high-to-low transition of the data line while the clock is high is defined as the Start condition (S). A low-to-high transition of the data line while the clock is high is defined as the Stop condition (P) (see Figure 11).

Figure 11. Start and Stop Conditions

8.5.7 System Configuration

A device generating a message is a transmitter; a device receiving is the receiver. The device that controls the message is the master and the devices which are controlled by the master are the slaves (see Figure 12).

Figure 12. System Configuration

8.5.8 Acknowledge

The number of data bytes transferred between the Start and the Stop conditions from transmitter to receiver is not limited. Each byte of eight bits is followed by one acknowledge bit. The acknowledge bit is a high level put on the bus by the transmitter, whereas the master generates an extra acknowledge related clock pulse.

A slave receiver which is addressed must generate an acknowledge after the reception of each byte. Also a master must generate an acknowledge after the reception of each byte that has been clocked out of the slave transmitter. The device that acknowledges has to pull down the SDA line during the acknowledge clock pulse, so that the SDA line is stable low during the high period of the acknowledge related clock pulse; set-up time and hold time must be taken into account.

A master receiver must signal an end of data to the transmitter by not generating an acknowledge on the last byte that has been clocked out of the slave. In this event, the transmitter must leave the data line high to enable the master to generate a Stop condition.

Figure 13. Acknowledge on I²C Bus

Figure 14. Write to a Specific Register

Figure 15. Write to All Registers Using Auto-Increment

Figure 16. Multiple Writes to Individual Brightness Registers Only Using the Auto-Increment Feature

Figure 17. Read All Registers With the Auto-Increment Feature

A. In this example, four TLC59108Fs are used with the same sequence sent to each.

B. ALLCALL bit in MODE1 register is equal to 1 for this example.

C. OCH bit in MODE2 register is equal to 1 for this example.

Figure 18. LED All-Call I²C Bus Address Programming and LED All-Call Sequence Example

8.6.1 Control Register

Following the successful acknowledgment of the slave address, LED All Call address or LED Sub Call address, the bus master will send a byte to the TLC59108F, which will be stored in the Control register. The lowest 5 bits are used as a pointer to determine which register will be accessed (D[4:0]). The highest 3 bits are used as Auto-Increment flag and Auto-Increment options (AI[2:0]).

Figure 19. Control Register

When the Auto-Increment flag is set (AI2 = logic 1), the five low order bits of the Control register are automatically incremented after a read or write. This allows the user to program the registers sequentially. Four different types of Auto-Increment are possible, depending on AI1 and AI0 values.

AI[2:0] = 000 is used when the same register must be accessed several times during a single I²C bus communication, for example, changes the brightness of a single LED. Data is overwritten each time the register is accessed during a write operation.

AI[2:0] = 100 is used when all the registers must be sequentially accessed, for example, power-up programming.

AI[2:0] = 101 is used when the four LED drivers must be individually programmed with different values during the same I²C bus communication, for example, changing color setting to another color setting.

AI[2:0] = 110 is used when the LED drivers must be globally programmed with different settings during the same I²C bus communication, for example, global brightness or blinking change.

AI[2:0] = 111 is used when individually and global changes must be performed during the same I²C bus communication, for example, changing color and global brightness at the same time.

Only the 5 least significant bits D[4:0] are affected by the AI[2:0] bits.

When Control register is written, the register entry point determined by D[4:0] is the first register that will be addressed (read or write operation), and can be anywhere between 0 0000 and 1 0001 (as defined in Table 2). When AI[2] = 1, the Auto-Increment flag is set and the rollover value at which the point where the register increment stops and goes to the next one is determined by AI[2:0]. See Table 1 for rollover values. For example, if the Control register = 1110 1100 (ECh), then the register addressing sequence will be (in hex):

04 → … → 11 → 02 → ... → 11 → 02 → … as long as the master keeps sending or reading data.

Table 2. Register Descriptions

8.6.2 Mode Register 1 (MODE1)

Table 3 describes Mode Register 1.

8.6.3 Mode Register 2 (MODE2)

Table 4 describes Mode Register 2.

8.6.4 Individual Brightness Control Registers (PWM0–PWM7)

Table 5 describes the Individual Brightness Control Registers.

A 97-kHz fixed-frequency signal is used for each output. Duty cycle is controlled through 256 linear steps from 00h (0% duty cycle = LED output off) to FFh (99.6% duty cycle = LED output at maximum brightness). Applicable to LED outputs programmed with LDRx = 10 or 11 (LEDOUT0 and LEDOUT1 registers).

duty cycle =

8.6.5 Group Duty Cycle Control Register (GRPPWM)

Table 6 describes the Group Duty Cycle Control Register .

When DMBLNK bit (MODE2 register) is programmed with logic 0, a 190-Hz fixed frequency signal is superimposed with the 97-kHz individual brightness control signal. GRPPWM is then used as a global brightness control allowing the LED outputs to be dimmed with the same value. The value in GRPFREQ is then a Don’t care.

General brightness for the 8 outputs is controlled through 256 linear steps from 00h (0% duty cycle = LED output off) to FFh (99.6% duty cycle = maximum brightness). Applicable to LED outputs programmed with LDRx = 11 (LEDOUT0 and LEDOUT1 registers).

When DMBLNK bit is programmed with logic 1, GRPPWM and GRPFREQ registers define a global blinking pattern, where GRPPWM and GRPFREQ registers define a global blinking pattern, where GRPFREQ contains the blinking period (from 24 Hz to 10.73 s) and GRPPWM the duty cycle (ON/OFF ratio in %).

Equation 1. Duty cycle =

8.6.6 Group Frequency Register (GRPFREQ)

Table 7 describes the Group Frequency Register.

GRPFREQ is used to program the global blinking period when DMBLNK bit (MODE2 register) is equal to 1. Value in this register is a Don’t care when DMBLNK = 0. Applicable to LED output programmed with LDRx = 11 (LEDOUT0 and LEDOUT1 registers).

Blinking period is controlled through 256 linear steps from 00h (41 ms, frequency 24 Hz) to FFh (10.73 s).

Equation 2. globalblinkingperiod =

8.6.7 LED Driver Output State Registers (LEDOUT0, LEDOUT1)

Table 8 describes the LED Driver Output State Registers.

LDRx = 00 : LED driver x is off (default power-up state).

LDRx = 01 : LED driver x is fully on (individual brightness and group dimming and blinking not controlled).

LDRx = 10 : LED driver x is individual brightness can be controlled through its PWMx register.

LDRx = 11 : LED driver x is individual brightness and group dimming/blinking can be controlled through its PWMx register and the GRPPWM registers.

8.6.8 I²C Bus Sub-Address Registers 1 to 3 (SUBADR1–SUBADR3)

Table 9 describes the Output Gain Control Register.

Sub-addresses are programmable through the I²C bus. Default power-up values are 92h, 94h, 98h and the device(s) will not acknowledge these addresses right after power-up (the corresponding SUBx bit in MODE1 register is equal to 0).

Once sub-addresses have been programmed to their right values, SUBx bits need to be set to 1 in order to have the device acknowledging these addresses (MODE1 register).

Only the 7 MSBs representing the I²C bus sub-address are valid. The LSB in SUBADRx register is a read-only bit (0).

When SUBx is set to 1, the corresponding I²C bus sub-address can be used during either an I²C bus read or write sequence.

8.6.9 LED All Call I²C Bus Address Register (ALLCALLADR)

Table 10 describes the LED All Call I²C Bus Address Register.

The LED All Call I²C-bus address allows all the TLC59108Fs in the bus to be programmed at the same time (ALLCALL bit in register MODE1 must be equal to 1 (power-up default state)). This address is programmable through the I²C-bus and can be used during either an I²C-bus read or write sequence. The register address can also be programmed as a Sub Call.

Only the 7 MSBs representing the All Call I²C-bus address are valid. The LSB in ALLCALLADR register is a read-only bit (0).

If ALLCALL bit = 0 (MODE1 register), the device does not acknowledge the address programmed in register ALLCALLADR.