9.3.1 Open-Circuit Detection

The TLC59116-Q1 LED open-circuit detection compares the effective current level I_OUT with the open load detection threshold current I_OUT,Th. If I_OUT is below the threshold I_OUT,Th the TLC59116-Q1 detects an open load condition. This error status can be read out as an error flag through the registers EFLAG1 and EFLAG2.

For open-circuit error detection, a channel must be on and the PWM must be off. See Table 1.

9.3.2 Overtemperature Detection and Shutdown

The TLC59116-Q1 LED is equipped with a global overtemperature sensor and 16 individual channel-selective overtemperature sensors.

• When the global sensor reaches the trip temperature, all output channels are shut down, and the error status is stored in the internal Error Status register of every channel. After shutdown, the channels automatically restart after cooling down, if the control signal (output latch) remains on. The stored error status is not reset after cooling down and can be read out as the error status code in registers EFLAG1 and EFLAG2.
• When one of the channel-specific sensors reaches trip temperature, only the affected output channel is shut down, and the error status is stored only in the internal Error Status register of the affected channel. After shutdown, the channel automatically restarts after cooling down, if the control signal (output latch) remains on. The stored error status is not reset after cooling down and can be read out as error status code in registers EFLAG1 and EFLAG2.

For channel-specific overtemperature error detection, a channel must be on.

The error flags of open-circuit and overtemperature are ORed to set the EFLAG1 and EFLAG2 registers.

The error status code because of overtemperature is reset when the host writes 1 to bit 7 of the MODE2 register. The host must write 0 to bit 7 of the MODE2 register to enable the overtemperature error flag. See Table 2.

9.3.3 Power-On Reset (POR)

When power is applied to V_CC, an internal power-on reset holds the TLC59116-Q1 in a reset condition until V_CC reaches V_POR. At this point, the reset condition is released and the TLC59116-Q1 registers, and I²C Bus state machine are initialized to their default states (all zeroes), causing all the channels to be deselected. Thereafter, V_CC must be lowered below 0.2 V to reset the device.

9.3.4 External Reset

A reset can be accomplished by holding the RESET pin low for a minimum of t_W. The TLC59116-Q1 registers and I²C state machine are held in their default states until the RESET input is again high.

This input requires a pullup resistor to V_CC if no active connection is used.

9.3.5 Software Reset

The Software Reset Call (SWRST Call) allows all the devices in the I²C Bus to be reset to the power-up state value through a specific I²C Bus command.

The SWRST Call function is defined as the following:

1. A Start command is sent by the I²C Bus master.
2. The reserved SWRST I²C Bus address 1101 011 with the R/W bit set to 0 (write) is sent by the I²C Bus master.
3. The TLC59116-Q1 device(s) acknowledge(s) after seeing the SWRST Call address 1101 0110 (D6h) only. If the R/W bit is set to 1 (read), no acknowledge is returned to the I²C Bus master.
4. Once the SWRST Call address has been sent and acknowledged, the master sends two bytes with two specific values (SWRST data byte 1 and byte 2):
   1. Byte1 = A5h: the TLC59116-Q1 acknowledges this value only. If byte 1 is not equal to A5h, the TLC59116-Q1 does not acknowledge it.
   2. Byte 2 = 5Ah: the TLC59116-Q1 acknowledges this value only. If byte 2 is not equal to 5Ah, the TLC59116-Q1 does not acknowledge it.

If more than two bytes of data are sent, the TLC59116-Q1 does not acknowledge any more.

5. Once the correct two bytes (SWRST data byte 1 and byte 2 only) have been sent and correctly acknowledged, the master sends a Stop command to end the SWRST Call. The TLC59116-Q1 then resets to the default value (power-up value) and is ready to be addressed again within the specified bus free time (t_BUF).

The I²C Bus master may interpret a non-acknowledge from the TLC59116-Q1 (at any time) as a SWRST Call Abort. The TLC59116-Q1 does not initiate a reset of its registers. This happens only when the format of the Start Call sequence is not correct.

9.3.6 Individual Brightness Control With Group Dimming/Blinking

A 97-kHz fixed-frequency signal with programmable duty cycle (8 bits, 256 steps) is used to control the individual brightness for each LED.

On top of this signal, one of the following signals can be superimposed (this signal can be applied to the four LED outputs):

• A lower 190-Hz fixed-frequency signal with programmable duty cycle (8 bits, 256 steps) provides a global brightness control.
• A programmable frequency signal from 24-Hz to 1/10.73 s (8 bits, 256 steps) provides a global blinking control. See Figure 9.

NOTE:

• Minimum pulse width for LEDn brightness control is 40 ns.
• Minimum pulse width for group dimming is 20.48 μs.
• When M = 1 (GRPPWM register value), the resulting LEDn Brightness Control + Group Dimming signal has two pulses of the LED Brightness Control signal (pulse width = n × 40 ns, with n defined in the PWMx register).
• This resulting Brightness + Group Dimming signal shows a resulting control signal with M = 4 (8 pulses).

Figure 9. Brightness and Group Dimming Signals

9.4.1 Active

Active mode occurs when one or more of the output channels is enabled.

9.4.2 Standby

Standby mode occurs when all output channels are disabled. Standby mode may be entered via I²C command or by pulling the RESET pin low.

9.5.1 Characteristics of the I²C Bus

The I²C Bus is for two-way two-line communication between different devices or modules. The two lines are a serial data line (SDA) and a serial clock line (SCL). Both lines must be connected to a positive supply via a pullup resistor when connected to the output stages of a device. Data transfer may be initiated only when the bus is not busy.

9.5.1.1 Bit Transfer

One data bit is transferred during each clock pulse. The data on the SDA line must remain stable during the high period of the clock pulse as changes in the data line at this time will be interpreted as control signals (see Figure 10).

Figure 10. Bit Transfer

9.5.1.2 Start and Stop Conditions

Both data and clock lines remain high when the bus is not busy. A high-to-low transition of the data line while the clock is high is defined as the Start condition (S). A low-to-high transition of the data line while the clock is high is defined as the Stop condition (P) (see Figure 11).

Figure 11. Start and Stop Conditions

9.5.1.3 Acknowledge

The number of data bytes transferred between the Start and the Stop conditions from transmitter to receiver is not limited. Each byte of eight bits is followed by one acknowledge bit. The acknowledge bit is a high level put on the bus by the transmitter, whereas the master generates an extra acknowledge related clock pulse. See Figure 12.

A slave receiver that is addressed must generate an acknowledge after the reception of each byte. Also a master must generate an acknowledge after the reception of each byte that has been clocked out of the slave transmitter. The device that acknowledges has to pull down the SDA line during the acknowledge clock pulse, so that the SDA line is stable low during the high period of the acknowledge related clock pulse; set-up time and hold time must be taken into account.

A master receiver must signal an end of data to the transmitter by not generating an acknowledge on the last byte that has been clocked out of the slave. In this event, the transmitter must leave the data line high to enable the master to generate a Stop condition. See Figure 13.

Figure 12. Acknowledge/Not Acknowledge on I²C Bus

Figure 13. Write to a Specific Register

See Table 4 for register definitions.

Figure 14. Write to All Registers Using Auto-Increment

Figure 15. Multiple Writes to Individual Brightness Registers Using Auto-Increment

Figure 16. Read All Registers Auto-Increment

A. In this example, several TLC59116-Q1 devices are used, and the same Sequence A is sent to each of them.

B. The ALLCALL bit in the MODE1 register is equal to 1 for this example.

C. The OCH bit in the MODE2 register is equal to 1 for this example.

Figure 17. LED All Call I²C Bus Address Programming and LED All Call Sequence

9.5.2 System Configuration

A device generating a message is a transmitter; a device receiving is the receiver. The device that controls the message is the master and the devices that are controlled by the master are the slaves (see Figure 18).

Figure 18. System Configuration

9.5.3 Device Address

Following a Start condition, the bus master must output the address of the slave it is accessing.

9.5.4 Regular I²C Bus Slave Address

The I²C Bus slave address of the TLC59116-Q1 is shown in Figure 19. To conserve power, no internal pullup resistors are incorporated on the hardware-selectable address pins, and they must be pulled high or low. For buffer management purposes, a set of sector information data should be stored.

Figure 19. Slave Address

The last bit of the address byte defines the operation to be performed. When set to logic 1, a read operation is selected. When set to logic 0, a write operation is selected.

9.5.5 LED All Call I²C Bus Address

• Default power-up value (ALLCALLADR register): D0h or 1101 000
• Programmable through I²C Bus (volatile programming)
• At power-up, LED All Call I²C Bus address is enabled. TLC59116-Q1 sends an ACK when D0h (R/W = 0) or D1h (R/W = 1) is sent by the master.

See LED All Call I2C Bus Address Register (ALLCALLADR) for more detail.

9.5.6 LED Sub Call I²C Bus Address

• Three different I²C Bus addresses can be used
• Default power-up values:
  • SUBADR1 register: D2h or 1101 001
  • SUBADR2 register: D4h or 1101 010
  • SUBADR3 register: D8h or 1101 100
• Programmable through I²C Bus (volatile programming)
• At power-up, Sub Call I²C Bus address is disabled. TLC59116-Q1 does not send an ACK when D2h (R/W = 0) or D3h (R/W = 1) or D4h (R/W = 0) or D5h (R/W = 1) or D8h (R/W = 0) or D9h (R/W = 1) is sent by the master.

See I2C Bus Subaddress Registers 1 to 3 (SUBADR1 to SUBADR3) for more detail.

9.5.7 Software Reset I²C Bus Address

The address shown in Figure 20 is used when a reset of the TLC59116-Q1 is performed by the master. The software reset address (SWRST Call) must be used with R/W = 0. If R/W = 1, the TLC59116-Q1 does not acknowledge the SWRST. See Software Reset for more detail.

Figure 20. Software Reset Address

9.5.8 Control Register

Following the successful acknowledgment of the slave address, LED All Call address or LED Sub Call address, the bus master sends a byte to the TLC59116-Q1, which is stored in the Control register. The lowest five bits are used as a pointer to determine which register is accessed (D[4:0]). The highest three bits are used as auto-increment flag and auto-increment options (AI[2:0]). See Figure 21.

Figure 21. Control Register

When the auto-increment flag is set (AI2 = logic 1), the five low order bits of the Control register are automatically incremented after a read or write. This allows the user to program the registers sequentially. Four different types of auto-increment are possible, depending on AI1 and AI0 values as shown in Table 3.

AI[2:0] = 000 is used when the same register must be accessed several times during a single I²C Bus communication, for example, changing the brightness of a single LED. Data is overwritten each time the register is accessed during a write operation.

AI[2:0] = 100 is used when all the registers must be sequentially accessed, for example, power-up programming.

AI[2:0] = 101 is used when the four LED drivers must be individually programmed with different values during the same I²C Bus communication, for example, changing a color setting to another color setting.

AI[2:0] = 110 is used when the LED drivers must be globally programmed with different settings during the same I²C Bus communication, for example, global brightness or blinking change.

AI[2:0] = 111 is used when individually and global changes must be performed during the same I²C Bus communication, for example, changing color and global brightness at the same time.

Only the five least significant bits D[4:0] are affected by the AI[2:0] bits.

When the Control register is written, the register entry point determined by D[4:0] is the first register that will be addressed (read or write operation), and can be anywhere between 0 0000 and 1 1011 (as defined in Table 4). When AI[2] = 1, the Auto-Increment flag is set and the rollover value at which the point where the register increment stops and goes to the next one is determined by AI[2:0]. See Table 3 for rollover values. For example, if the Control register = 1111 0100 (F4h), then the register addressing sequence will be (in hex):

14 → ... → 1B → 00 → ... → 13 → 02 → ... → 13 → 02 → ... as long as the master keeps sending or reading data.

Table 4. Register Descriptions

9.6.1 Mode Register 1 (MODE1)

Table 5 describes Mode Register 1.

9.6.2 Mode Register 2 (MODE2)

Table 6 describes Mode Register 2.

9.6.3 Brightness Control Registers 0 to 15 (PWM0 to PWM15)

Table 7 describes Brightness Control Registers 0 to 15.

A 97-kHz fixed frequency signal is used for each output. Duty cycle is controlled through 256 linear steps from 00h (0% duty cycle = LED output off) to FFh (99.6% duty cycle = LED output at maximum brightness). Applicable to LED outputs programmed with LDRx = 10 or 11 (LEDOUT0, LEDOUT1, LEDOUT2 and LEDOUT3 registers).

9.6.4 Group Duty Cycle Control Register (GRPPWM)

Table 8 describes the Group Duty Cycle Control Register.

When the DMBLNK bit (MODE2 register) is programmed with logic 0, a 190-Hz fixed-frequency signal is superimposed with the 97-kHz individual brightness control signal. GRPPWM is then used as a global brightness control, allowing the LED outputs to be dimmed with the same value. The value in GRPFREQ is then a Don't care.

General brightness for the 16 outputs is controlled through 256 linear steps from 00h (0% duty cycle = LED output off) to FFh (99.6% duty cycle = maximum brightness). This is applicable to LED outputs programmed with LDRx = 11 (LEDOUT0, LEDOUT1, LEDOUT2 and LEDOUT3 registers).

When DMBLNK bit is programmed with logic 1, the GRPPWM and GRPFREQ registers define a global blinking pattern, where GRPFREQ defines the blinking period (from 24-Hz to 10.73 s) and GRPPWM defines the duty cycle (ON/OFF ratio in %).

9.6.5 Group Frequency Register (GRPFREQ)

Table 9 describes the Group Frequency Register.

GRPFREQ is used to program the global blinking period when the DMBLNK bit (MODE2 register) is equal to 1. Value in this register is a Don't care when DMBLNK = 0. This is applicable to LED output programmed with LDRx = 11 (LEDOUT0, LEDOUT1, LEDOUT2 and LEDOUT3 registers).

The blinking period is controlled through 256 linear steps from 00h (41 ms, frequency 24 Hz) to FFh (10.73 s).

Global blinking period (seconds) = (GFRQ[7:0] + 1) / 24

9.6.6 LED Driver Output State Registers 0 to 3 (LEDOUT0 to LEDOUT3)

Table 10 describes LED Driver Output State Registers 0 to 3.

LDRx = 00: LED driver x is off (default power-up state).

LDRx = 01: LED driver x is fully on (individual brightness and group dimming/blinking not controlled).

LDRx = 10: LED driver x is individual brightness can be controlled through its PWMx register.

LDRx = 11: LED driver x is individual brightness and group dimming/blinking can be controlled through its PWMx register and the GRPPWM registers.

9.6.7 I²C Bus Subaddress Registers 1 to 3 (SUBADR1 to SUBADR3)

Table 11 describes I²C Bus Subaddress Registers 1 to 3.

Subaddresses are programmable through the I²C Bus. Default power-up values are D2h, D4h, D8h. The TLC59116-Q1 does not acknowledge these addresses immediately after power-up (the corresponding SUBx bit in MODE1 register is equal to 0).

Once subaddresses have been programmed to valid values, the SUBx bits (MODE1 register) must be set to 1 to allows the device to acknowledge these addresses.

Only the 7 MSBs representing the I²C Bus subaddress are valid. The LSB in SUBADRx register is a read-only bit (0).

When SUBx is set to 1, the corresponding I²C Bus subaddress can be used during either an I²C Bus read or write sequence.

9.6.8 LED All Call I²C Bus Address Register (ALLCALLADR)

Table 12 describes the LED All Call I²C Bus Address Register.

The LED All Call I²C Bus address allows all the TLC59116-Q1 devices in the bus to be programmed at the same time (ALLCALL bit in register MODE1 must be equal to 1, which is the power-up default state). This address is programmable through the I²C Bus and can be used during either an I²C Bus read or write sequence. The register address can also be programmed as a Sub Call.

Only the seven MSBs representing the All Call I²C bus address are valid. The LSB in ALLCALLADR register is a read-only bit (0).

If ALLCALL bit = 0, the device does not acknowledge the address programmed in register ALLCALLADR.

9.6.9 Output Gain Control Register (IREF)

Table 13 describes the Output Gain Control Register.

IREF determines the voltage gain (VG), which affects the voltage at the REXT terminal and indirectly the reference current (I_ref) flowing through the external resistor at terminal REXT. Bit 0 is the Current Multiplier (CM) bit, which determines the ratio I_OUT,target/I_ref. Each combination of VG and CM sets a Current Gain (CG).

• VG: the relationship between {HC,CC[0:5]} and the voltage gain is calculated as shown:

VG = (1 + HC) × (1 + D/64) / 4

D = CC0 × 2⁵ + CC1 × 2⁴ + CC2 × 2³ + CC3 × 2² + CC4 × 2¹ + CC5 × 2⁰

Where HC is 1 or 0, and D is the binary value of CC[0:5]. So, the VG could be regarded as a floating-point number with 1-bit exponent HC and 6-bit mantissa CC[0:5]. {HC,CC[0:5]} divides the programmable voltage gain (VG) into 128 steps and two sub-bands:

Low-voltage subband (HC = 0): VG = 1/4 to 127/256, linearly divided into 64 steps

High-voltage subband (HC = 1): VG = 1/2 to 127/128, linearly divided into 64 steps

• CM: In addition to determining the ratio I_OUT,target/I_ref, CM limits the output current range.

High Current Multiplier (CM = 1): I_OUT,target/I_ref = 15, suitable for output current range I_OUT = 10 mA to 120 mA.

Low Current Multiplier (CM = 0): I_OUT,target/I_ref = 5, suitable for output current range I_OUT = 5 mA to 40 mA

• CG: The total Current Gain is defined as:

V_REXT = 1.26 V × VG

I_ref = V_REXT/R_ext, if the external resistor (R_ext) is connected to ground.

I_OUT,target = I_ref × 15 × 3^{CM – 1} = 1.26 V/R_ext × VG × 15 × 3^CM – 1 = (1.26 V/R_ext × 15) × CG

CG = VG × 3^CM – 1

Therefore, CG = (1/12) to (127/128), divided into 256 steps.

Examples

• IREF Code {CM, HC, CC[0:5]} = {1,1,111111}

VG = 127/128 = 0.992 and CG = VG × 3⁰ = VG = 0.992

• IREF Code {CM, HC, CC[0:5]} = {1,1,000000}

VG = (1 + 1) × (1 + 0/64)/4 = 1/2 = 0.5, and CG = 0.5

• IREF Code {CM, HC, CC[0:5]} = {0,0,000000}

VG = (1 + 0) × (1 + 0/64)/4 = 1/4, and CG = (1/4) × 3^–1 = 1/12

After power-on, the default value of the Configuration Code {CM, HC, CC[0:5]} is {1,1,111111}. Therefore, VG = CG = 0.992. The relationship between the Configuration Code and the Current Gain is shown in Figure 22.

Figure 22. Current Gain vs Configuration Code

9.6.10 Error Flags Registers (EFLAG1, EFLAG2)

Table 14 describes Error Flags Registers 1 and 2.