TLC59213x 8-Bit Parallel In and Out Darlington Source Driver With Latch

1 Features

Output Current on Each Channel
(I_OUT Max = –500 mA)
V_CE(sus) = 13.2 V
Input Compatible With TTL/5-V CMOS
Clear (CLR) and Clock (CLK) TTL/CMOS Control Inputs
CLR Control Input to Off the Output
Darlington Source Driver
Clock Input Up to 1 MHz
Enhanced Hold Time (t_h) on TLC59213A
Temperature Range: –40°C to 85°C

2 Applications

Lamp and Display (LED)
Hammer
Relay

3 Description

The TLC59213 and TLC59213A are 8-bit source drivers with input latch with CLK input and CLR to set the output OFF. The TLC59213 and TLC59213A have large output source currents up to 500 mA with Darlington transistor and collectors tied to V_CC. These feature make the device optimum level of driving the matrix of ink jet printer head, LEDs, and the scan-side of resistor's matrix. The TLC59213 and TLC59213A differ only in the Data Hold Time Specification (t_h).

The clamp diode is between output and ground for switching inductive load.

All inputs are TTL/CMOS, which enable to any logic-level inputs such as MCU, CPU or SN74LV594 (serial to parallel) and the output enable LED matrix display. It can also be used with another device sink driver such as TLC59210, TLC59211 and TLC59212.

Device Information⁽¹⁾

PART NUMBER	PACKAGE	BODY SIZE (NOM)
TLC59213 TLC59213A	PDIP (20)	24.33 mm × 6.35 mm
TLC59213 TLC59213A	TSSOP (20)	6.50 mm × 4.40 mm

For all available packages, see the orderable addendum at the end of the data sheet.

Typical Application Diagram÷

4 Revision History

Changes from A Revision (March 2010) to B Revision

Added Pin Configuration and Functions section, ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information section Go

5 Pin Configuration and Functions

N or PW Package

20-Pin PDIP or TSSOP

Top View

Pin Functions

PIN		I/O	DESCRIPTION
NAME	NO.	I/O	DESCRIPTION
CLR	1	I	Direct clear of output
D1	2	I	Input control to the current source driver
D2	3	I	Input control to the current source driver
D3	4	I	Input control to the current source driver
D4	5	I	Input control to the current source driver
D5	6	I	Input control to the current source driver
D6	7	I	Input control to the current source driver
D7	8	I	Input control to the current source driver
D8	9	I	Input control to the current source driver
CLK	10	I	Clock to positive edge triggered D flipflops
GND	11	—	Ground
Y8	12	O	Output to load
Y7	13	O	Output to load
Y6	14	O	Output to load
Y5	15	O	Output to load
Y4	16	O	Output to load
Y3	17	O	Output to load
Y2	18	O	Output to load
Y1	19	O	Output to load
V_cc	20	I	Supply voltage

6 Specifications

6.1 Absolute Maximum Ratings⁽¹⁾

over operating free-air temperature range (unless otherwise noted)

			MIN	MAX	UNIT
V_DD	Supply voltage		–0.5	15	V
V_I	Input voltage		–0.5	V_CC + 0.5	V
	Collector-emitter voltage		–0.5	15	V
I_O	Peak output current			–500	mA
I_IK	Input clamp current	V_I < 0 V		–20	mA
I_OK	Output clamp current	V_O < 0 V		–500	mA
T_stg	Storage temperature		–65	150	°C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

6.2 ESD Ratings

			VALUE	UNIT
V_(ESD)	Electrostatic discharge	Human body model (HBM), per ANSI/ESDA/JEDEC JS-001⁽¹⁾	±2000	V
V_(ESD)	Electrostatic discharge	Charged-device model (CDM), per JEDEC specification JESD22-C101⁽²⁾	±1000	V

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

				MIN	MAX	UNIT
V_CC	Supply voltage			4.5	13.2	V
V_IH	High-level input voltage			2		V
V_IL	Low-level input voltage				0.8	V
I_O	Output current (8 channel)	N package	Duty cycle < 10%		400	mA
		N package	Duty cycle < 50%		200
		PW package	Duty cycle < 10%		350
		PW package	Duty cycle < 50%		170
T_A	Operating free-air temperature			–40	85	°C

6.4 Electrical Characteristics

over recommended operating free-air temperature range (unless otherwise noted)

PARAMETER		TEST CONDITIONS		MIN	TYP	MAX	UNIT
I_CEX	Output leakage current	V_CC = 13.2 V, Outputs off				2	µA
V_CE(sus)	Output saturation voltage	I_OUT = –350 mA				2.35	V
		I_OUT = –225 mA				2.15
		I_OUT = –100 mA				1.96
I_I	Input current	V_CC = 13.2 V, V_I = 0 or 13.2 V				1	µA
V_f	Clamp forward voltage	I_f = –350 mA		–2			V
I_CC	Supply current	V_CC = 13.2 V, V_I = 0 or 13.2 V	All outputs OFF		4.6	13	mA
I_CC	Supply current	V_CC = 13.2 V, V_I = 0 or 13.2 V	All outputs ON		4.8	13	mA
C_I	Input capacitance					10	pF

6.5 Timing Requirements

over recommended operating free-air temperature range (unless otherwise noted), see Figure 3

					MIN	UNIT
t_su	Setup time	D before CLK ↑			50	ns
t_su	Setup time	CLR high before CLK ↑			50	ns
t_h	Hold time	D after CLK ↑	TLC59213, TLC59213A	T_A = -40°C to 85°C	50	ns
			TLC59213	T_A = 0°C to 70°C	25
			TLC59213A	T_A = 0°C to 70°C, V_CC = 4.5 V to 5.5 V	15
			TLC59213A	T_A = 0°C to 70°C, V_CC = 10.8 V to 13.2 V	19
t_w	Pulse width	CLK, CLR			100	ns

6.6 Switching Characteristics

over operating free-air temperature range (unless otherwise noted), see Figure 3

PARAMETER		FROM (INPUT)	TO (OUTPUT)	TEST CONDITIONS	T_A = 25°C			T_A = –40°C to 85°C		UNIT
PARAMETER		FROM (INPUT)	TO (OUTPUT)	TEST CONDITIONS	MIN	TYP	MAX	MIN	MAX	UNIT
t_PLH	Propagation delay time, low-to-high level output	CLK	Y	RL = 25 Ω, C_L = 15 pF		107	200		250	ns
t_PHL	Propagation delay time, high-to-low level output	CLK	Y	RL = 25 Ω, C_L = 15 pF		111	200		250	ns
t_PHLR	Propagation delay time, high-to-low level output	CLR	Y	RL = 25 Ω, C_L = 15 pF		104	200		250	ns

6.7 Typical Characteristics

Figure 1. Maximum Output Current vs Duty Cycle (TSSOP (PW) Package)

Figure 2. Maximum Output Current vs Duty Cycle (DIP (N) Package)