SLVS973A September 2009 – July 2015 TLC5926-Q1 , TLC5927-Q1
PRODUCTION DATA.
MIN | MAX | UNIT | ||
---|---|---|---|---|
VDD(2)(3)(4) | Supply voltage | 0 | 7 | V |
VI(2)(5) | Input voltage | –0.4 | VDD + 0.4 | V |
VO(2)(6)(7) | Output voltage | –0.5 | 20 | V |
IOUT | Output current | 120 | mA | |
IGND | GND terminal current | 1920 | mA | |
TA | Free-air operating temperature | –40 | 125 | °C |
TJ | Operating junction temperature | –40 | 150 | °C |
Tstg | Storage temperature | –55 | 150 | °C |
VALUE | UNIT | |||||
---|---|---|---|---|---|---|
V(ESD) | Electrostatic discharge | Human body model (HBM), per AEC Q100-002(1) | ±2000 | V |
MIN | MAX | UNIT | ||||
---|---|---|---|---|---|---|
VDD | Supply voltage | 3 | 5.5 | V | ||
VO | Supply voltage to the output pins | OUT0–OUT15 | 17 | V | ||
IO | Output current | DC test circuit | VO ≥ 0.6 V | 5 | mA | |
VO ≥ 1 V | 120 | |||||
IOH | High-level output current | SDO shorted to GND | –1 | mA | ||
IOL | Low-level output current | SDO shorted to GND | 1 | mA | ||
VIH | High-level input voltage | CLK, OE(ED2), LE(ED1), and SDI | 0.7 × VDD | VDD | V | |
VIL | Low-level input voltage | CLK, OE(ED2), LE(ED1), and SDI | 0 | 0.3 × VDD | V |
THERMAL METRIC(1)(2) | TLC592x-Q1 | UNIT | ||
---|---|---|---|---|
PWP (HTSSOP) | ||||
24 PINS | ||||
RθJA | Junction-to-ambient thermal resistance | Mounted on JEDEC 1-layer board (JESD 51-3), No airflow | 63.9 | °C/W |
Mounted on JEDEC 4-layer board (JESD 51-7), No airflow | 42.7 | |||
Mounted on JEDEC 4-layer board (JESD 51-5), No airflow | 39.7 | |||
RθJC(top) | Junction-to-case (top) thermal resistance | 23.4 | °C/W | |
RθJB | Junction-to-board thermal resistance | 20.4 | °C/W | |
ψJT | Junction-to-top characterization parameter | 0.7 | °C/W | |
ψJB | Junction-to-board characterization parameter | 20.2 | °C/W | |
RθJC(bot) | Junction-to-case (bottom) thermal resistance | 3.9 | °C/W |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | ||
---|---|---|---|---|---|---|---|
VO | Supply voltage to the output pins | 17 | V | ||||
IO | Output current | VO ≥ 0.6 V | 5 | mA | |||
VO ≥ 1 V | 120 | ||||||
VIH | High-level input voltage | 0.7 × VDD | VDD | V | |||
VIL | Low-level input voltage | GND | 0.3 × VDD | ||||
Ileak | Output leakage current | TLC5926-Q1, VOH = 17 V | TJ = 25°C | 0.5 | μA | ||
TJ = 125°C | 1 | ||||||
TLC5927-Q1, VOH = 17 V | TJ = 25°C | 0.5 | |||||
TJ = 125°C | 5 | ||||||
VOH | High-level output voltage | SDO, IOL = –1 mA | VDD – 0.4 | V | |||
VOL | Low-level output voltage | SDO, IOH = 1 mA | 0.4 | V | |||
IO(1)(2) | Output current 1 | VOUT = 0.6 V, Rext = 720 Ω, CG = 0.992 | 26 | mA | |||
Output current error, die-to-die | IOL = 26 mA, VO = 0.6 V, Rext = 720 Ω, TJ = 25°C | ±6% | |||||
Output current error, channel-to-channel | IOL = 26 mA, VO = 0.6 V, Rext = 720 Ω, TJ = 25°C | ±6% | |||||
IO(1)(2) | Output current 2 | VO = 0.8 V, Rext = 360 Ω, CG = 0.992 | 52% | mA | |||
Output current error, die-to-die | IOL = 52 mA, VO = 0.8 V, Rext = 360 Ω, TJ = 25°C | ±6% | |||||
Output current error, channel-to-channel | IOL = 52 mA, VO = 0.8 V, Rext = 360 Ω, TJ = 25°C | ±6% | |||||
IOUT vs VOUT | Output current vs output voltage regulation | VO = 1 V to 3 V, IO = 26 mA | ±0.1 | %/V | |||
IOUT vs VDD | Output current vs supply voltage | VDD = 3 V to 5.5 V, IO = 26 mA/120 mA | ±1 | ||||
Pullup resistance | OE(ED2) | 250 | 500 | 800 | kΩ | ||
Pulldown resistance | LE(ED1) | 250 | 500 | 800 | kΩ | ||
Tsd | Overtemperature shutdown(2) | 150 | 175 | 200 | °C | ||
Thys | Restart temperature hysteresis | 15 | °C | ||||
IOUT,Th | Threshold current for open error detection | IOUT,target = 5 mA to 120 mA | 0.5 × Itarget% | ||||
VOUT,TTh | Trigger threshold voltage for short-error detection (TLC5927 only) | IOUT,target = 5 mA to 120 mA | 2.3 | 2.6 | 3.2 | V | |
VOUT,RTh | Return threshold voltage for short-error detection (TLC5927 only) | IOUT,target = 5 mA to 120 mA | 1.9 | V | |||
IDD | Supply current | OUT0–OUT15 = off, Rext = Open, OE = VIH | 10 | mA | |||
OUT0–OUT15 = off, Rext = 720 Ω, OE = VIH | 14 | ||||||
OUT0–OUT15 = off, Rext = 360 Ω, OE = VIH | 18 | ||||||
OUT0–OUT15 = off, Rext = 180 Ω, OE = VIH | 20 | ||||||
OUT0–OUT15 = on, Rext = 720 Ω, OE = VIL | 14 | ||||||
OUT0–OUT15 = on, Rext = 360 Ω, OE = VIL | 18 | ||||||
OUT0–OUT15 = on, Rext = 180 Ω, OE = VIL | 20 |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | ||
---|---|---|---|---|---|---|---|
VO | Supply voltage to the output pins | 17 | V | ||||
IO | Output current | VO ≥ 0.6 V | 5 | mA | |||
VO ≥ 1 V | 120 | ||||||
VIH | High-level input voltage | 0.7 × VDD | VDD | V | |||
VIL | Low-level input voltage | GND | 0.3 × VDD | ||||
Ileak | Output leakage current | TLC5926, VOH = 17 V | TJ = 25°C | 0.5 | μA | ||
TJ = 125°C | 1 | ||||||
TLC5927, VOH = 17 V | TJ = 25°C | 0.5 | |||||
TJ = 125°C | 5 | ||||||
VOH | High-level output voltage | SDO, IOL = –1 mA | VDD – 0.4 | V | |||
VOL | Low-level output voltage | SDO, IOH = 1 mA | 0.4 | V | |||
IO(1)(1)(1) | Output current 1 | VOUT = 0.6 V, Rext = 720 Ω, CG = 0.992 | 26 | mA | |||
Output current error, die-to-die | IOL = 26 mA, VO = 0.6 V, Rext = 720 Ω, TJ = 25°C | ±6% | |||||
Output current error, channel-to-channel | IOL = 26 mA, VO = 0.6 V, Rext = 720 Ω, TJ = 25°C | ±6% | |||||
IO(2)(1)(2) | Output current 2 | VO = 0.8 V, Rext = 360 Ω, CG = 0.992 | 52 | mA | |||
Output current error, die-to-die | IOL = 52 mA, VO = 0.8 V, Rext = 360 Ω, TJ = 25°C | ±6% | |||||
Output current error, channel-to-channel | IOL = 52 mA, VO = 0.8 V, Rext = 360 Ω, TJ = 25°C | ±6% | |||||
IOUT vs VOUT | Output current vs output voltage regulation | VO = 1 V to 3 V, IO = 26 mA | ±0.1 | %/V | |||
IOUT vs VDD | Output current vs supply voltage | VDD = 3 V to 5.5 V, IO = 26 mA/120 mA | ±1 | ||||
Pullup resistance | OE(ED2) | 250 | 500 | 800 | kΩ | ||
Pulldown resistance | LE(ED1) | 250 | 500 | 800 | kΩ | ||
Tsd | Overtemperature shutdown(2) | 150 | 175 | 200 | °C | ||
Thys | Restart temperature hysteresis | 15 | °C | ||||
IOUT,Th | Threshold current for open error detection | IOUT,target = 5 mA to 120 mA | 0.5 × Itarget% | ||||
VOUT,TTh | Trigger threshold voltage for short-error detection (TLC5927 only) | IOUT,target = 5 mA to 120 mA | 2.3 | 2.6 | 3.2 | V | |
VOUT,RTh | Return threshold voltage for short-error detection (TLC5927 only) | IOUT,target = 5 mA to 120 mA | 1.9 | V | |||
IDD | Supply current | OUT0–OUT15 = off, Rext = Open, OE = VIH | 11 | mA | |||
OUT0–OUT15 = off, Rext = 720 Ω, OE = VIH | 17 | ||||||
OUT0–OUT15 = off, Rext = 360 Ω, OE = VIH | 18 | ||||||
OUT0–OUT15 = off, Rext = 180 Ω, OE = VIH | 25 | ||||||
OUT0–OUT15 = on, Rext = 720 Ω, OE = VIL | 17 | ||||||
OUT0–OUT15 = on, Rext = 360 Ω, OE = VIL | 18 | ||||||
OUT0–OUT15 = on, Rext = 180 Ω, OE = VIL | 25 |
MIN | MAX | UNIT | |||
---|---|---|---|---|---|
tw(L) | LE(ED1) pulse duration | Normal mode | 20 | ns | |
tw(CLK) | CLK pulse duration | Normal mode | 20 | ns | |
tw(OE) | OE(ED2) pulse duration | Normal mode | 1000 | ns | |
tsu(D) | Setup time for SDI | Normal mode | 7 | ns | |
th(D) | Hold time for SDI | Normal mode | 3 | ns | |
tsu(L) | Setup time for LE(ED1) | Normal mode | 18 | ns | |
th(L) | Hold time for LE(ED1) | Normal mode | 18 | ns | |
tw(CLK) | CLK pulse duration | Error Detection mode | 20 | ns | |
tw(ED2) | OE(ED2) pulse duration | Error Detection mode | 2000 | ns | |
tsu(ED1) | Setup time for LE(ED1) | Error Detection mode | 7 | ns | |
th(ED1) | Hold time for LE(ED1) | Error Detection mode | 10 | ns | |
tsu(ED2) | Setup time for OE(ED2) | Error Detection mode | 7 | ns | |
th(ED2) | Hold time for OE(ED2) | Error Detection mode | 10 | ns | |
fCLK | Clock frequency | Cascade operation, VDD = 3 V to 5.5 V | 30 | MHz |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
tPLH1 | Low-to-high propagation delay time, CLK to OUTn | VIH = VDD, VIL = GND, Rext = 360 Ω, VL = 4 V, RL = 44 Ω, CL = 70 pF, CG = 0.992 | 35 | 65 | 105 | ns |
tPLH2 | Low-to-high propagation delay time, LE(ED1) to OUTn | 35 | 65 | 105 | ns | |
tPLH3 | Low-to-high propagation delay time, OE(ED2) to OUTn | 35 | 65 | 105 | ns | |
tPLH4 | Low-to-high propagation delay time, CLK to SDO | 20 | 45 | ns | ||
tPHL1 | High-to-low propagation delay time, CLK to OUTn | 200 | 300 | 470 | ns | |
tPHL2 | High-to-low propagation delay time, LE(ED1) to OUTn | 200 | 300 | 470 | ns | |
tPHL3 | High-to-low propagation delay time, OE(ED2) to OUTn | 200 | 300 | 470 | ns | |
tPHL4 | High-to-low propagation delay time, CLK to SDO | 20 | 40 | ns | ||
tw(CLK) | Pulse duration, CLK | 20 | ns | |||
tw(L) | Pulse duration LE(ED1) | 20 | ns | |||
tw(OE) | Pulse duration, OE(ED2) | 1000 | ns | |||
tw(ED2) | Pulse duration, OE(ED2) in Error Detection mode | 2 | μs | |||
th(ED1,ED2) | Hold time, LE(ED1), and OE(ED2) | 10 | ns | |||
th(D) | Hold time, SDI | 5 | ns | |||
tsu(D,ED1,ED2) | Setup time, SDI, LE(ED1), and OE(ED2) | 7 | ns | |||
th(L) | Hold time, LE(ED1), Normal mode | 18 | ns | |||
tsu(L) | Setup time, LE(ED1), Normal mode | 18 | ns | |||
tr | Rise time, CLK(1) | 500 | ns | |||
tf | Fall time, CLK(1) | 500 | ns | |||
tor | Rise time, outputs (off) | 245 | ns | |||
tof | Rise time, outputs (on) | 600 | ns | |||
fCLK | Clock frequency | Cascade operation | 30 | MHz |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
tPLH1 | Low-to-high propagation delay time, CLK to OUTn | VIH = VDD, VIL = GND, Rext = 360 Ω, VL = 4 V, RL = 44 Ω, CL = 70 pF, CG = 0.992 | 27 | 65 | 95 | ns |
tPLH2 | Low-to-high propagation delay time, LE(ED1) to OUTn | 27 | 65 | 95 | ns | |
tPLH3 | Low-to-high propagation delay time, OE(ED2) to OUTn | 27 | 65 | 95 | ns | |
tPLH4 | Low-to-high propagation delay time, CLK to SDO | 20 | 30 | ns | ||
tPHL1 | High-to-low propagation delay time, CLK to OUTn | 180 | 300 | 445 | ns | |
tPHL2 | High-to-low propagation delay time, LE(ED1) to OUTn | 180 | 300 | 445 | ns | |
tPHL3 | High-to-low propagation delay time, OE(ED2) to OUTn | 180 | 300 | 445 | ns | |
tPHL4 | High-to-low propagation delay time, CLK to SDO | 20 | 30 | ns | ||
tw(CLK) | Pulse duration, CLK | 20 | ns | |||
tw(L) | Pulse duration LE(ED1) | 20 | ns | |||
tw(OE) | Pulse duration, OE(ED2) | 1000 | ns | |||
tw(ED2) | Pulse duration, OE(ED2) in Error Detection mode | 2 | μs | |||
th(ED1,ED2) | Hold time, LE(ED1), and OE(ED2) | 10 | ns | |||
th(D) | Hold time, SDI | 3 | ns | |||
tsu(D,ED1,ED2) | Setup time, SDI, LE(ED1), and OE(ED2) | 4 | ns | |||
th(L) | Hold time, LE(ED1), Normal mode | 15 | ns | |||
tsu(L) | Setup time, LE(ED1), Normal mode | 15 | ns | |||
tr | Rise time, CLK(1) | 500 | ns | |||
tf | Fall time, CLK(1) | 500 | ns | |||
tor | Rise time, outputs (off) | 245 | ns | |||
tof | Rise time, outputs (on) | 570 | ns | |||
fCLK | Clock frequency | Cascade operation | 30 | MHz |