SBVS199C June   2012  – January 2024 TLC59283

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configurations
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 Storage Conditions
    3. 5.3 ESD Ratings
    4. 5.4 Recommended Operating Conditions
    5. 5.5 Thermal Information
    6. 5.6 Electrical Characteristics
    7. 5.7 Timing Characteristics
    8. 5.8 Timing Diagrams
    9. 5.9 Typical Characteristics
  7. 6 Parameter Measurement Information
    1. 6.1 Pin-equivalent Input and Output Schematic Diagrams
    2. 6.2 Test Circuits
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Constant Sink Current Value Setting
      2. 7.3.2 Constant-current Driver On or Off Control
      3. 7.3.3 Noise Reduction
        1. 7.3.3.1 Internal Pre-Charge FET
        2. 7.3.3.2 Improve Output Control Loop Stability
  9. 8 Register Configuration
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Performance Plots
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Third-Party Products Disclaimer
    2. 10.2 Documentation Support
      1. 10.2.1 Related Documentation
    3. 10.3 Receiving Notification of Documentation Updates
    4. 10.4 Support Resources
    5. 10.5 Trademarks
    6. 10.6 Electrostatic Discharge Caution
    7. 10.7 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

4 Pin Configurations

GUID-2B434755-CE7F-4F81-8201-8D0F60DC96F7-low.gif Figure 4-1 DBQ PackageSSOP-24 and QSOP-24(top view)
GUID-63ABC29E-2352-47DA-A175-E20128E75B8C-low.gif Figure 4-2 RGE PackageQFN-24(top view)
NOTE: Thermal pad is not connected to GND internally. The thermal pad must be connected to GND with the printed circuit board (PCB) pattern.
Table 4-1 Pin Functions
PIN I/O DESCRIPTION
NAME NUMBER
DBQ RGE
BLANK 21 18 I All outputs empty (blank); Schmitt buffer input. When BLANK is high, all constant-current outputs (OUT0 to OUT15) are forced off and all pre-charge FETs are turned on. When BLANK is low, all constant-current outputs are controlled by the data in the output on or off data latch and all pre-charge FETs are turned off. This pin is internally pulled up to VCC with a 500kΩ (typ) resistor.
GND 1 22 — Power ground
IREF 23 20 I/O Constant-current value setting, the OUT0 to OUT15 sink constant-current outputs are set to the desired values by connecting an external resistor between IREF and GND.
LAT 4 1 I Level-triggered latch; Schmitt buffer input. The data in the 16-bit shift register continue to transfer to the output on or off data latch while LAT is high. Therefore, if the data in the 16-bit shift register are changed when LAT is high, the data in the data latch are also changed. The data in the data latch are held when LAT is low. This pin is internally pulled down to GND with a 500kΩ (typ) resistor.
OUT0 5 2 O Constant-current output. Each output can be tied together with others to increase the constant-current. Different voltages can be applied to each output.
OUT1 6 3 O Constant-current output
OUT2 7 4 O Constant-current output
OUT3 8 5 O Constant-current output
OUT4 9 6 O Constant-current output
OUT5 10 7 O Constant-current output
OUT6 11 8 O Constant-current output
OUT7 12 9 O Constant-current output
OUT8 13 10 O Constant-current output
OUT9 14 11 O Constant-current output
OUT10 15 12 O Constant-current output
OUT11 16 13 O Constant-current output
OUT12 17 14 O Constant-current output
OUT13 18 15 O Constant-current output
OUT14 19 16 O Constant-current output
OUT15 20 17 O Constant-current output
SCLK 3 24 I Serial data shift clock; Schmitt buffer input.
All data in the 16-bit shift register are shifted toward the MSB by a 1-bit SCLK synchronization.
SIN 2 23 I Serial data input for driver on or off control; Schmitt buffer input.
When SIN is high, the LSB is set to '1' for only one SCLK input rising edge. If two SCLK rising edges are input while SIN is high, then the 16-bit shift register LSB and LSB+1 are set to '1'. When SIN is low, the LSB is set to '0' at the SCLK input rising edge.
SOUT 22 19 O Serial data output. This output is connected to the 16-bit shift register MSB. SOUT data changes at the SCLK rising edge.
VCC 24 21 — Power-supply voltage