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  • TLC59291 8/16-Channel, Constant Current LED Driver with 7-bit Brightness Control Low Quiescent Current and Full Self Diagnosis for LED Lamp

    • SLVSA96A September   2015  – March 2016 TLC59291

      PRODUCTION DATA.  

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  • TLC59291 8/16-Channel, Constant Current LED Driver with 7-bit Brightness Control Low Quiescent Current and Full Self Diagnosis for LED Lamp
  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Characteristics
    7. 6.7 Timing Diagrams
    8. 6.8 Typical Characteristics
  7. 7 Parameter Measurement Information
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Maximum Constant Sink Current
      2. 8.3.2 Global Brightness Control (BC) Function
      3. 8.3.3 Thermal Shutdown (TSD) and Thermal Error Flag (TEF)
      4. 8.3.4 Pre-Thermal Warning (PTW)
      5. 8.3.5 Current Reference Terminal - IREF Terminal - Short Flag (ISF)
      6. 8.3.6 Noise Reduction
    4. 8.4 Device Functional Modes
      1. 8.4.1 Blank Mode Selection (BLKMS)
      2. 8.4.2 Power-Save Mode
      3. 8.4.3 LED Open Detection (LOD)
      4. 8.4.4 LED Short Detection (LSD)
      5. 8.4.5 Invisible Detection Mode (IDM)
      6. 8.4.6 Output Leakage Detection (OLD)
      7. 8.4.7 Status Information Data (SID)
    5. 8.5 Register Maps
      1. 8.5.1 Register and Data Latch Configuration
        1. 8.5.1.1 Common Shift Register
        2. 8.5.1.2 Output On/Off Data Latch
        3. 8.5.1.3 Control Data Latch
        4. 8.5.1.4 Output On/Off Data Write Timing and Output Control
        5. 8.5.1.5 Function Control Data Writing
        6. 8.5.1.6 Function Control (FC) Data
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
    2. 12.2 Community Resources
    3. 12.3 Trademarks
    4. 12.4 Electrostatic Discharge Caution
    5. 12.5 Glossary
  13. 13Mechanical, Packaging, and Orderable Information
  14. IMPORTANT NOTICE

Package Options

Mechanical Data (Package|Pins)
  • RGE|24
    • MPQF124G
Thermal pad, mechanical data (Package|Pins)
  • RGE|24
    • QFND008AA
Orderable Information
  • slvsa96a_oa
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    • Expanded reading width
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DATA SHEET

TLC59291 8/16-Channel, Constant Current LED Driver with 7-bit Brightness Control Low Quiescent Current and Full Self Diagnosis for LED Lamp

1 Features

  • 8/16 Constant-Current Sink Output Channels with On/Off Control
  • Current Capability:
    • 1 - 40 mA (VCC ≤ 3.6 V)
    • 1 - 50 mA (VCC > 3.6 V)
  • Global Brightness Control: 7-Bit (128 Steps)
  • Power-Supply Voltage Range: 3 V to 5.5 V
  • LED Power-Supply Voltage: Up to 10 V
  • Constant-Current Accuracy:
    • Channel-to-Channel = ±3% (Typical)
    • Device-to-Device = ±2% (Typical)
  • Low Quiescent Current
  • SOUT can be Configured for 8-Channel or 16-Channel Output
  • LED Open Detection (LOD)/LED Short Detection (LSD) with Invisible Detection Mode (IDM)
  • Output Leakage Detection (OLD) Detects 3 µA Leak
  • Pre-Thermal Warning (PTW)
  • Thermal Shutdown (TSD)
  • Current Reference Terminal Short Flag (ISF)
  • Power-Save Mode with 10-µA Consumption
  • Undervoltage Lockout Sets the Default Data
  • 2-ns Delayed Switching Between Each Channel Minimizes Inrush Current
  • Operating Temperature: –40°C to 85°C

2 Applications

  • Industry LED Indicator
  • Illumination
  • LED Video Display

3 Description

The TLC59291 is a 8/16-channel constant current sink LED driver. Each channel can be turned on-off by writing data to an internal register. The constant current value of all 16 channels is set by a single external resistor and 128 steps for the global brightness control (BC).

The TLC59291 has six type error flags: LED open detection (LOD), LED short detection (LSD), output leak detection (OLD), reference terminal short detection (ISF), Pre thermal warning (PTW) and thermal error flag (TEF). In addition, the LOD and LSD functions have invisible detection mode (IDM) that can detect those errors even when the output is off. The error detection results can be read via a serial interface port.

The TLC59291 has low quiescent current in normal mode, it also has a power-save mode that sets the total current consumption to 10 uA (typical) when all outputs are off.

Device Information(1)

PART NUMBER PACKAGE BODY SIZE (NOM)
TLC59291 VQFN (24) 4.00mm x 4.00mm
  1. For all available packages, see the orderable addendum at the end of the data sheet.

Typical Application Circuit (Multiple Daisy Chained TLC59291s)

TLC59291 typ_app_slvsa96.gif

4 Revision History

Changes from * Revision (September 2015) to A Revision

  • Changed Features From: Channel-to-Channel = ±1% (Typical) To: Channel-to-Channel = ±3% (Typical)Go
  • Deleted device number TLC5929 From the Electrical Characteristics tableGo
  • Changed ΔIOL(C0) Test Condition in Electrical Characteristics From: BC = 7Fh, RIREF = 1.6 kΩ To: BC = 0Eh, RIREF = 3.6 kΩ, Go
  • Changed the ΔIOL(C1) values in Electrical Characteristics From: TYP = ±2%, MAX = ±4% To TYP = 1% , MAX = ÷3%: Go
  • Deleted device number TLC5929 From the Switching Characteristics tableGo
  • Changed text From: "with the 1-bit data" To: "with the 16-bit data" in the Function Control Data Writing section Go

5 Pin Configuration and Functions

RGE Package
24-Pin VQFN
(Top View)
TLC59291 po_RGE_slvsa96.gif

Pin Functions

PIN I/O DESCRIPTION
NAME NO.
BLANK 18 I BLANK PIN, has two configures:
When FC9(BLANK Mode) = 0, Blank pin worked as SOUT select pin:
  1. When BLANK = Low, SOUT is connected to the bit 7 of the 16-bit shift register, worked as 8ch device;
  2. When BLANK = High, SOUT is connected to the bit 15 of the 16-bit shift register, worked as 16ch device;

When FC9(BLANK Mode) = 1, Blank pin worked as OUTPUT enable pin;
  1. When BLANK = Low, all constant current outputs are controlled by the on/off control data in the data latch.
  2. When BLANK = High, all OUTx are forced off
GND 22 — Ground
IREF 20 I/O Maximum current programming terminal.
A resistor connected between IREF and GND sets the maximum current for every constant-current output. When this terminal is directly connected to GND, all outputs are forced off. The external resistor should be placed close to the device and must be in the range of 1.32 kΩ to 66 kΩ.
LAT 1 I Data latch.
The rising edge of LAT latches the data from the common shift register into the output on/off data latch. At the same time, the data in the common shift register are replaced with SID, which is selected by SIDLD. See the Output On/Off Data Latch section and Status Information Data (SID) section for more details.
OUT0 2 O Constant-current sink outputs.
Multiple outputs can be configured in parallel to increase the constant-current capability. Different voltages can be applied to each output.
OUT1 3 O
OUT2 4 O
OUT3 5 O
OUT4 6 O
OUT5 7 O
OUT6 8 O
OUT7 9 O
OUT8 10 O
OUT9 11 O
OUT10 12 O
OUT11 13 O
OUT12 14 O
OUT13 15 O
OUT14 16 O
OUT15 17 O
SCLK 24 I Serial data shift clock.
Data present on SIN are shifted to the LSB of the 16-bit shift register with the SCKI rising edge. Data in the shift register are shifted toward the MSB at each SCLK rising edge. The MSB data of the common shift register appear on SOUT.
SIN 23 I Serial data input for the 16-bit common shift register.
When SIN is high, a '1' is written to the LSB of the common shift register at the rising edge of SCLK.
SOUT 19 O Serial data output of the 16-bit common shift register.
When FC9(BLANK Mode) = 0 and BLANK = LOW;
SOUT is connected to the bit 7 of the 16-bit shift register. Data are clocked out at the SCLK rising edge.
In other case:
SOUT is connected to the bit 15 of the 16-bit shift register. Data are clocked out at the SCLK rising edge.
VCC 21 — Power-supply voltage

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted) (1)
VALUE UNIT
MIN MAX
Supply voltage, VCC(2) –0.3 6 V
Input voltage SIN, SCLK, LAT, BLANK, IREF –0.3 VCC + 0.3 V
Output voltage SOUT –0.3 VCC + 0.3 V
OUT0 to OUT15 –0.3 11 V
Output current (DC) OUT0 to OUT15 65 mA
Operating junction temperature, TJ (max) 150 °C
Storage temperature, TSTG –55 150 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltages are with respect to device ground terminal.

6.2 ESD Ratings

VALUE UNIT
V(ESD) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±4000 V
Charged-device model (CDM), per JEDEC specification JESD22-C101(2) ±2000
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

At TA= –40°C to 85°C, unless otherwise noted.
PARAMETER TEST CONDITIONS MIN NOM MAX UNIT
DC Characteristics: VCC = 3 V to 5.5 V
VCC Supply voltage 3 3.3 5.5 V
VO Voltage applied to output OUT0 to OUT15 10 V
VIH High-level input voltage SIN, SCLK, LAT, BLANK 0.7 × VCC VCC V
VIL Low-level input voltage SIN, SCLK, LAT, BLANK GND 0.3 × VCC V
IOH High-level output current SOUT –2 mA
IOL Low-level output current SOUT 2 mA
IOLC Constant output sink current OUT0 to OUT15 3 V ≤ VCC ≤ 3.6 V 40 mA
OUT0 to OUT15 3.6 V < VCC ≤ 5.5 V 50 mA
TA Operating free-air temperature range –40 85 °C
TJ Operating junction temperature range –40 125 °C
AC Characteristics: VCC = 3 V to 5.5 V
fCLK (SCLK) Data shift clock frequency SCLK 33 MHz
tWH0 Pulse duration
(see Figure 1 and Figure 3)		 SCLK 10 ns
tWL0 SCLK 10 ns
tWH1 LAT 20 ns
tWH2 BLANK 40 ns
tWL2 BLANK 40 ns
tSU0 Setup time
(see Figure 1, Figure 3 and Figure 4)		 SIN to SCLK↑ 5 ns
tSU1 LAT↑ to SCLK↑ 200 ns
tSU2 SCLK ↓to LAT↑ 10 ns
tH0 Hold time
(see Figure 1, Figure 3, and Figure 13)		 SIN to SCLK↑ 3 ns
tH1 LAT↑ to SCLK↑ 10 ns
tH2 LAT↑ to SCLK ↓ 40 ns

6.4 Thermal Information

THERMAL METRIC(1) TLC59291 UNIT
RGE (VQFN)
24 PINS
RθJA Junction-to-ambient thermal resistance 38.1 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 45.3
RθJB Junction-to-board thermal resistance 16.9
ψJT Junction-to-top characterization parameter 0.9
ψJB Junction-to-board characterization parameter 16.9
RθJC(bot) Junction-to-case (bottom) thermal resistance 6.2
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.

6.5 Electrical Characteristics

At VCC = 3 V to 5.5 V and TA = –40°C to 85°C. Typical values at VCC = 3.3 V and TA = 25°C, unless otherwise noted.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VOH High-level output voltage IOH = –2 mA at SOUT VCC – 0.4 VCC V
VOL Low-level output voltage IOL = 2 mA at SOUT 0.4 V
VLOD LED open detection threshold All OUTn = on 0.25 0.30 0.35 V
VLSD0 LED short detection threshold All OUTn = on, detection voltage code = 0h 0.32 × VCC 0.35 × VCC 0.38 × VCC V
VLSD1 All OUTn = on, detection voltage code = 1h 0.42 × VCC 0.45 × VCC 0.48 × VCC V
VLSD2 All OUTn = on, detection voltage code = 2h 0.52 × VCC 0.55 × VCC 0.58 × VCC V
VLSD3 All OUTn = on, detection voltage code = 3h 0.62 × VCC 0.65 × VCC 0.68 × VCC V
VIREF Reference voltage output RIREF = 1.3 kΩ 1.175 1.205 1.235 V
IIN Input current VIN = VCC or GND at SIN, SCLK, LAT, and BLANK –1 1 μA
ICC0 Supply current (VCC) SIN/SCLK/LAT = Low, BLANK = High, all OUTn = off,
VOUTn = 0.8 V, BC = 7Fh, RIREF = open		 2 3 mA
ICC1 SIN/SCLK/LAT = Low, BLANK = High, all OUTn = off,
VOUTn = 0.8 V, BC = 7Fh, RIREF = 3.6 kΩ
(IOUT = 18.3 mA target)		 5 7 mA
ICC2 SIN/SCLK/LAT/BLANK =Low, All OUTn = on,
VOUTn = 0.8 V, BC = 7Fh, RIREF = 3.6 kΩ
(IOUT = 18.3 mA target)		 5 7 mA
ICC3 SIN/SCLK/LAT/BLANK =Low, All OUTn = on,
VOUTn = 0.8 V, BC = 0Eh, RIREF = 1.6 kΩ
(IOUT = 2 mA target)		 3 4 mA
ICC4 SIN/SCLK/LAT/BLANK = Low, All OUTn = on,
VOUTn = 0.8 V, BC = 7Fh, RIREF = 1.6 kΩ
(IOUT = 41.3 mA target)		 9 11 mA
ICC5 VCC = 5 V, SIN/SCLK/LAT/BLANK = Low,
All OUTn = on, VOUTn = 0.8 V, BC = 7Fh,
RIREF = 1.3 kΩ (IOUT = 50.8 mA target)		 11 14 mA
ICC6 VCC = 5 V, SIN/SCLK/LAT/BLANK = Low,
VOUTn = 0.8 V, BC = 7Fh, RIREF = 1.3 kΩ
(IOUT = 50.8 mA target), all output data off with power-save mode enabled		 10 40 µA
IOL(C0) Constant output sink current
(OUT0 to OUT15, see Figure 28)		 All OUTn = on, VOUTn = VOUTfix = 0.8 V, BC = 7Fh,
RIREF = 1.6 kΩ		 38.5 41.3 44.1 mA
IOL(C1) VCC = 5 V, All OUTn = on, VOUTn = VOUTfix = 1 V,
BC = 7Fh, RIREF = 1.3 kΩ		 47.3 50.8 54.3 mA
IOL(KG0) Output leakage current
(OUT0 to OUT15, see Figure 28)		 BLANK = high, VOUTn = VOUTfix = 10 V, RIREF = 1.6 kΩ TJ = 25°C 0.1 μA
IOL(KG1) TJ = 85°C(1) 0.2 μA
IOL(KG2) TJ = 125°C(1) 0.3 0.8 μA
ΔIO(LC0) Constant-current error
(channel-to-channel, OUT0 to OUT15)(2) 		All OUTn = on, VOUTn = VOUTfix = 0.8 V, BC = 0Eh,
RIREF = 3.6 kΩ, TA = 25°C 		±3% ±6%
ΔIOL(C1) Constant-current error
(device-to-device, OUT0 to OUT15)(3) 		All OUTn = on, VOUTn = VOUTfix = 0.8 V, BC = 7Fh,
RIREF = 1.6 kΩ, TA = 25°C		 ±1% ±3%
ΔIOL(C2) Line regulation(4) All OUTn = on, VOUTn = VOUTfix = 0.8 V, BC = 7Fh,
RIREF = 1.6 kΩ		 ±0.1 ±1 %/V
ΔIOL(C3) Load regulation(5) All OUTn = on, VOUTn = 0.8 V to 3 V, VOUTfix = 0.8 V,
BC = 7Fh, RIREF = 1.6 kΩ 		±0.5 ±3 %/V
TTEF Thermal error flag threshold Junction temperature(1) 150 165 180 °C
THYS Thermal error flag hysteresis Junction temperature(1) 5 10 20 °C
TPTW Pre-thermal warning threshold Junction temperature(1) 125 138 150 °C
(1) Not tested; specified by design.
(2) The deviation of each output from the average of OUT0 to OUT15 constant-current. Deviation is calculated by the formula: TLC59291 q_delta01_slvsa96.gif .
(3) The deviation of the OUT0 to OUT15 constant-current average from the ideal constant-current value. Deviation is calculated by the formula:
TLC59291 q_delta02_slvsa96.gif
Ideal current is calculated by the formula: TLC59291 q_iout_ideal_slvsa96.gif
(4) Line regulation is calculated by the formula:
TLC59291 q_line_slvsa96.gif
(5) Load regulation is calculated by the equation:
TLC59291 q_load_slvsa96.gif

6.6 Switching Characteristics

At VCC = 3 V to 5.5 V, TA = –40°C to 85°C, CL = 15 pF, RL = 82 Ω, RIREF = 1.3 kΩ, and VLED = 5 V.
Typical values at VCC = 3.3 V and TA = 25°C, unless otherwise noted.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
tR0 Rise time At SOUT 10 15 ns
tR1 At OUTn, BC = 7Fh 40 60 ns
tF0 Fall time At SOUT 10 15 ns
tF1 At OUTn, BC = 7Fh 40 60 ns
tD0 Propagation delay SCLK↑ to SOUT↑↓ 8 22 ns
tD1 LAT↑ or BLANK↑↓ to OUT0 sink current on/off,
BC = 7Fh		 35 65 ns
tD2 OUTn on/off to OUTn + 1 on/off, BC = 7Fh 2 6 ns
tD3 LAT↑ to power-save mode by data writing for all output off 400 ns
tD4 SCLK↑ to normal mode operation 100 µs
tD5 BLANK↑↓ to SOUT↑↓ when BLANK MODE=0 100 ns
tON_ERR Output on-time error(1) Output on/off data = all '1',
BLANK low pulse = 40 ns, BC = 7Fh		 –30 20 ns
fOSC Internal oscillator frequency 12 20 28 MHz
(1) Output on-time error (tON_ERR) is calculated by the formula: tON_ERR (ns) = tOUT_ON – 40 ns. tOUT_ON is the actual on-time of OUTn.

6.7 Timing Diagrams

TLC59291 tim_input_bvs159.gif
1. Input pulse rise and fall time is 1 ns to 3 ns.
Figure 1. Input Timing
TLC59291 tim_output_bvs159.gif
1. Input pulse rise and fall time is 1 ns to 3 ns.
Figure 2. Output Timing
TLC59291 writ_output_timg_BM1_slvsa96.gif
1.

NOINDENT:

On/off latched data is '1'.
2.

NOINDENT:

On/off latched data change from '1' to '0' at second LAT signal.
3.

NOINDENT:

On/off latched data change from '0' to '1' at second LAT signal.
4.

NOINDENT:

On/off latched data is '0'.
Figure 3. Write for ON/Off Data and Output Timing (BLANK Mode = 1)
TLC59291 writ_output_timg_BM0_slvsa96.gif
1.

NOINDENT:

If the on/off latched data is changed from “0” to “1” at 1’st LAT signal, changed from “1” to “0” at second LAT signal.
2.

NOINDENT:

If the on/off latched data is changed from “0” to “1” at 1’st LAT signal, changed from “1” to “1” at second LAT signal.
3.

NOINDENT:

If the on/off latched data is changed from “1” to “0” at 1’st LAT signal, changed from “0” to “1” at second LAT signal.
4.

NOINDENT:

if the on/off latched data is “0”.
Figure 4. Write for On/Off Data and Output Timing (BLANK Mode = 0)
TLC59291 pwr_save_mode_tim_slvsa96.gif Figure 5. Power-Save Mode
TLC59291 PTW_TEF_TSD_timg_slvsa96.gif Figure 6. PTW/TEF/TSD Timing (LOD Selected)
TLC59291 pwr_save_mode_slvsa96.gif Figure 7. Power-Save Mode Timing
TLC59291 IDM_oper_timg_enable_slvsa96.gif Figure 8. IDM Operation Timing with LOD Selected and IDM Enabled
TLC59291 IDM_oper_timg_disable_slvsa96.gif Figure 9. IDM Operation Timing with LOD Selected and IDM Disabled
TLC59291 SID_read_timing_slvsa96.gif Figure 10. SID Read Timing
TLC59291 on_off_contrl_data_BM1_slvsa96.gif
1.

NOINDENT:

On/off latch data is '1'.
2.

NOINDENT:

On/off latch data change from '1' to '0' at second LAT signal.
3.

NOINDENT:

On/off latch data is change from '0' to '1' at second LAT signal.
4.

NOINDENT:

On/off latch data is '0'.
Figure 11. On-Off Control Data Write Timing (BLANK Mode = 1)
TLC59291 on_off_contrl_data_BM0_slvsa96.gif
1. If the on/off latched data is changed from “0” to “1” at 1’st LAT signal, changed from “1” to “0” at 2’nd LAT signal.
2. If the on/off latched data is changed from “0” to “1” at 1’st LAT signal, changed from “1” to “1” at 2’nd LAT signal.
3. If the on/off latched data is changed from “1” to “0” at 1’st LAT signal, changed from “0” to “1” at 2’nd LAT signal.
4. If the on/off latched data is “0”.
Figure 12. On-Off Control Data Write Timing (BLANK Mode = 0)
TLC59291 func_contrl_data_write_slvsa96.gif Figure 13. Function Control Data Write Timing

6.8 Typical Characteristics

At TA = 25°C, unless otherwise noted.
TLC59291 tc_riref-iolcmax_slvsa96.gif
Figure 14. Reference Resistor vs Output Current
TLC59291 tc_iout-vout_33v_tmp_slvsa96.gif
VCC = 3.3 V BC = 7Fh RIREF = 1.58 kΩ
VOUTn = 0.8 V
Figure 16. OUTn Current vs Output Voltage
TLC59291 tc_iout-vout_5v_tmp_slvsa96.gif
VCC = 5 V BC = 7Fh RIREF = 1.28 kΩ
VOUTn = 1 V
Figure 18. OUTn Current vs Output Voltage
TLC59291 tc_constant-tmp_slvsa96.gif
RIREF = 1.28 kΩ VOUTn = 0.8 V
Figure 20. Constant-Current Error
vs Ambient Temperature (Channel-to-Channel)
TLC59291 tc_icc-iout_slvsa96.gif
BC = 7Fh RIREF = 1.6 kΩ SIN = 17.5 MHz
SCLK = 35 MHz All Outpts on
Figure 22. Supply Current
vs Output Current Set by RIREF
TLC59291 tc_icc_power_save-tmp_slvsa96.gif
BC = 7Fh RIREF = 1.6 kΩ SIN = SCLK = Low
Power-Save Mode
Figure 24. Supply Current in Power-Save Mode
vs Ambient Temperature
TLC59291 tc_iout-vout_33v_slvsa96.gif
VCC = 3.3 V BC = 7Fh VOUTn = 0.8 V
Figure 15. OUTn Current vs Output Voltage
TLC59291 tc_iout-vout_5v_slvsa96.gif
VCC = 5 V BC = 7Fh VOUTn = 0.8 V
50 mA = 1 V
Figure 17. OUTn Current vs Output Voltage
TLC59291 tc_constant-iout_riref_slvsa96.gif
BC = 7Fh VOUTn = 0.8 V 50 mA = 1 V
Figure 19. Constant-Current Error
vs Output CurrenT set by RIREF or BC Data (Channel-to-Channel)
TLC59291 tc_global_bc_linearity_slvsa96.gif
Figure 21. Global Brightness
Control Linearity
TLC59291 tc_icc-tmp_slvsa96.gif
BC = 7Fh RIREF = 1.6 kΩ SIN = 17.5 MHz
SCLK = 35 MHz All Outpts on
Figure 23. Supply Current
vs Ambient Temperature
TLC59291 tc_constant-waveform_slvsa96.gif
VCC = 3.3 V BC = 7Fh RIREF = 1.6 kΩ
VLED = 5 V RL = 100 Ω CL = 15 pF
Figure 25. Constant-Current Output
Voltage Waveform

7 Parameter Measurement Information

TLC59291 tac_rise_fall_outn_bvs120.gif
1.

NOINDENT:

CL includes measurement probe and jig capacitance.
Figure 26. Rise Time and Fall Time Test Circuit for OUTn
TLC59291 tac_rise_fall_sout_bvs120.gif
1.

NOINDENT:

CL includes measurement probe and jig capacitance.
Figure 27. Rise Time and Fall Time Test Circuit for SOUT
TLC59291 tac_test_outn_bvs152.gif Figure 28. Constant-Current Test Circuit for OUTn

 
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