SLVSCE7A May   2014  – September 2014 TLC5958

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Typical Application Circuit (Multiple Daisy-Chained TLC5958s)
  5. 5 Revision History
  6. 6 Description (Continued)
  7. 7 Pin Configuration and Functions
  8. 8 Specifications
    1. 8.1 Absolute Maximum Ratings
    2. 8.2 Handling Ratings
    3. 8.3 Recommended Operating Conditions
    4. 8.4 Thermal Information
    5. 8.5 Electrical Characteristics
    6. 8.6 Typical Characteristics
  9. 9 Parameter Measurement Information
    1. 9.1 Pin Equivalent Input and Output Schematic Diagrams
      1. 9.1.1 Test Circuits
    2. 9.2 Timing Diagrams
  10. 10Detailed Description
    1. 10.1 Overview
    2. 10.2 Functional Block Diagram
    3. 10.3 Device Functional Modes
      1. 10.3.1  Brightness Control (BC) Function
      2. 10.3.2  Color Brightness Control (CC) Function
      3. 10.3.3  Select RIREF For a Given BC
      4. 10.3.4  Choosing BC/CC For a Different Application
        1. 10.3.4.1 Example 1: Red LED Current is 20mA, Green LED Needs 12mA, Blue LED needs 8mA
        2. 10.3.4.2 Example 2: Red LED Current is 5mA, Green LED Needs 2mA, Blue LED Needs 1mA.
      5. 10.3.5  LED Open Detection (LOD)
      6. 10.3.6  Power Save Mode (PSM)
      7. 10.3.7  Internal Pre-Charge FET
      8. 10.3.8  Thermal Shutdown (TSD)
      9. 10.3.9  IREF Resistor Short Protection (ISP)
      10. 10.3.10 Noise Reduction
  11. 11Application and Implementation
  12. 12Power Supply Recommendations
  13. 13Layout
    1. 13.1 Layout Guidelines
    2. 13.2 Layout Example
  14. 14Device and Documentation Support
    1. 14.1 Trademarks
    2. 14.2 Electrostatic Discharge Caution
    3. 14.3 Glossary
  15. 15Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

13 Layout

13.1 Layout Guidelines

  1. Place the decoupling capacitor near the VCC pin and GND plane.
  2. Place the current programming resistor Riref close to IREF pin and IREFGND pin.
  3. Route the GND pattern as widely as possible for large GND currents. Maximum GND current is approximately 1.2A
  4. Routing between the LED cathode side and the device OUTXn pin should be as short and straight as possible to reduce wire inductance.
  5. The PowerPAD™ must be connected to GND plane because the pad is used as power ground pin internally, there will be large current flow through this pad when all channels turn on. Furthermore, this pad should be connected to a heat sink layer by thermal via to reduce device temperature. One suggested thermal via pattern is shown as below. For more information about suggested thermal via pattern and via size, see " PowerPAD Thermally Enhanced Package", SLMA002G.

13.2 Layout Example

via_layout_SLVSCE7.gif