SLVSCE7A May   2014  – September 2014 TLC5958

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Typical Application Circuit (Multiple Daisy-Chained TLC5958s)
  5. 5 Revision History
  6. 6 Description (Continued)
  7. 7 Pin Configuration and Functions
  8. 8 Specifications
    1. 8.1 Absolute Maximum Ratings
    2. 8.2 Handling Ratings
    3. 8.3 Recommended Operating Conditions
    4. 8.4 Thermal Information
    5. 8.5 Electrical Characteristics
    6. 8.6 Typical Characteristics
  9. 9 Parameter Measurement Information
    1. 9.1 Pin Equivalent Input and Output Schematic Diagrams
      1. 9.1.1 Test Circuits
    2. 9.2 Timing Diagrams
  10. 10Detailed Description
    1. 10.1 Overview
    2. 10.2 Functional Block Diagram
    3. 10.3 Device Functional Modes
      1. 10.3.1  Brightness Control (BC) Function
      2. 10.3.2  Color Brightness Control (CC) Function
      3. 10.3.3  Select RIREF For a Given BC
      4. 10.3.4  Choosing BC/CC For a Different Application
        1. 10.3.4.1 Example 1: Red LED Current is 20mA, Green LED Needs 12mA, Blue LED needs 8mA
        2. 10.3.4.2 Example 2: Red LED Current is 5mA, Green LED Needs 2mA, Blue LED Needs 1mA.
      5. 10.3.5  LED Open Detection (LOD)
      6. 10.3.6  Power Save Mode (PSM)
      7. 10.3.7  Internal Pre-Charge FET
      8. 10.3.8  Thermal Shutdown (TSD)
      9. 10.3.9  IREF Resistor Short Protection (ISP)
      10. 10.3.10 Noise Reduction
  11. 11Application and Implementation
  12. 12Power Supply Recommendations
  13. 13Layout
    1. 13.1 Layout Guidelines
    2. 13.2 Layout Example
  14. 14Device and Documentation Support
    1. 14.1 Trademarks
    2. 14.2 Electrostatic Discharge Caution
    3. 14.3 Glossary
  15. 15Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7 Pin Configuration and Functions

56 Pin
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Pin Functions

PIN I/O DESCRIPTION
NAME NO.
GCLK 29 I Grayscale(GS) pulse width modulation (PWM) reference clock control for OUTXn.
Each GCLK rising edge increase the GS counter by1 for PWM control.
GND ThermalPad – Power ground. The thermal pad must be soldered to GND on PCB.
IREF 1 – Maximum constant-current value setting. The OUTR0 to OUTB15 maximum constant output current are set to the desired values by connecting an external resistor between IREF and IREFGND. See equation 1 for more detail. The external resistor should be placed close to the device.
IREFGND 56 – Analog ground. Dedicated ground pin for the external IREF resistor. This pin should be connected to analog ground trace which is connected to power ground near the common GND point of board.
LAT 27 I The LAT falling edge latches the data from the common shift register into the GS data memory or Function control(FC) register FC1 or FC2.
OUTR0-R15 8, 11, 14, 17, 20, 23, 30, 33, 36, 39, 44, 47, 50, 53 ,2, 5 O Constant current output for RED LED. Multiple outputs can be tied together to increase the constant current capability. Different voltages can be applied to each output. These outputs are turned on-off by GCLK signal and the data in GS data memory.
OUTG0-G15 9, 12, 15, 18, 21, 24, 31, 34, 37, 40, 45, 48, 51, 54, 3, 6 O Constant current output for GREEN LED. Multiple outputs can be tied together to increase the constant current capability. Different voltages can be applied to each output. These outputs are turned on-off by GCLK signal and the data in GS data memory.
OUTB0-B15 10, 13, 16, 19, 22, 25, 32, 35, 38, 41, 46, 49, 52, 55, 4, 7 O Constant current output for BLUE LED. Multiple outputs can be tied together to increase the constant current capability. Different voltages can be applied to each output. These outputs are turned on-off by GCLK signal and the data in GS data memory.
SCLK 28 I Serial data shift clock. Data present on SIN are shifted to the 48-bit common shift register LSB with the SCLK rising edge. Data in the shift register are shifted towards the MSB at each SCLK rising edge. The common shift register MSB appears on SOUT.
SIN 26 I Serial data input of the 48-bit common shift register. When SIN is high level, the LSB is set to '1' for only one SCLK input rising edge. If two SCLK rising edges are input while SIN is high, then the 48-bit shift register LSB and LSB+1 are set to '1'. When SIN is low, the LSB is set to '0' at the SCLK input rising edge.
SOUT 42 O Serial data output of the 48-bit common shift register. SOUT is connected to the MSB of the register.
VCC 43 – Power-supply voltage.