Place the decoupling capacitor near the VCC pin and GND plane.
Place the current programming resistor RIREF close to IREF pin and IREFGND pin.
Route the GND pattern as widely as possible for large GND currents. Maximum GND current is approximately 1.2 A.
Routing between the LED cathode side and the device OUTXn pin should be as short and straight as possible to reduce wire inductance.
The PowerPAD™ must be connected to GND plane because the pad is used as power ground pin internally, there is a large current flow through this pad when all channels turn on. Furthermore, this pad should be connected to a heat sink layer by thermal via to reduce device temperature. One suggested thermal via pattern is shown in the Device Layout Example. For more information about suggested thermal via pattern and via size, see PowerPAD Thermally Enhanced Package, SLMA002G.
MOSFETS must be placed in the in the middle of the board, which should be laid out as symmetrically as possible.