SLVSCO9A August 2015 – August 2015 TLC6C5712-Q1
PRODUCTION DATA.
MIN | MAX | UNIT | ||
---|---|---|---|---|
Input voltage | VCC | –0.3 | 7 | V |
IREF, LATCH, PWMx, SCK, SDI | –0.3 | VCC | ||
SENSE | –0.3 | 10 | ||
Output voltage | ERR open-drain output | –0.3 | 7 | V |
OUTx power DMOS drain-to-source voltage | –0.3 | 10 | ||
SDO | –0.3 | VCC | ||
Ground | PGND | –0.3 | 0.3 | V |
Operating ambient temperature, TA | –40 | 125 | °C | |
Operating junction temperature, TJ | –40 | 150 | °C | |
Storage temperature range, Tstg | –55 | 150 | °C |
VALUE | UNIT | ||||
---|---|---|---|---|---|
V(ESD) | Electrostatic discharge | Human body model (HBM), per AEC Q100-002(1) | ±2000 | V | |
Charged device model (CDM), per AEC Q100-011 | All pins | ±500 | V | ||
Corner pins (1, 14, 15, and 28) | ±750 |
MIN | NOM | MAX | UNIT | |||
---|---|---|---|---|---|---|
VCC | Supply input voltage | 3 | 5.5 | V | ||
VI | Input voltage | LATCH, PWMx, SCK, SDI, SDO | 0 | 5.5 | V | |
ERR, SENSE | 0 | 7 | ||||
VO | Output voltage | OUTx for x = 0 to 11 | 0.5 | 7 | V | |
VIL | Input logic-low voltage | LATCH, PWMx, SCK, SDI | 0.28 VCC | 0.3 VCC | 0.33 VCC | V |
VIH | Input logic-high voltage | LATCH, PWMx, SCK, SDI | 0.38 VCC | 0.4 VCC | 0.43 VCC | V |
TA | Ambient operating temperature | –40 | 125 | ºC | ||
TJ | Junction operating temperature | –40 | 150 | ºC |
THERMAL METRIC(1) | TLC6C5712-Q1 | UNIT | |
---|---|---|---|
PWP (HTSSOP) | |||
28 PINS | |||
RθJA | Junction-to-ambient thermal resistance | 39 | °C/W |
RθJC(top) | Junction-to-case (top) thermal resistance | 19.5 | °C/W |
RθJB | Junction-to-board thermal resistance | 16.1 | °C/W |
ψJT | Junction-to-top characterization parameter | 0.5 | °C/W |
ψJB | Junction-to-board characterization parameter | 15.9 | °C/W |
RθJC(bot) | Junction-to-case (bottom) thermal resistance | 1.7 | °C/W |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
POWER SUPPLIES (VCC, PGND, GND) | ||||||
ICC | Supply current | VCC = 5 V, PWM = H, RREF = 20.5 kΩ | 3 | 4.5 | mA | |
VCC = 3.3 V | 2.5 | 4 | ||||
V(POR-rising) | Power-on reset voltage, rising | Rising threshold | 2.6 | 2.7 | 2.8 | V |
V(POR-falling) | Power-on reset voltage, falling | Falling threshold | 2.4 | 2.5 | 2.6 | V |
V(POR-hyst) | POR threshold hysteresis | 0.2 | V | |||
LOGIC INPUTS (PWMx, SDI, LATCH, SCK) | ||||||
V(HYS) | Input logic hysterisis | VCC = 5 V or 3.3 V | 0.1 VCC | V | ||
Ilkg | Input leakage current | VI = VCC | –1 | 1 | µA | |
RPU | PWM pullup resistance | 105 | 150 | 230 | kΩ | |
CONTROL OUTPUTS (ERR, IREF, SDO) | ||||||
V(ERR) | ERR pin open-drain voltage drop | I(ERR) = 4 mA, VCC = 3.3 V–5 V | 0.1 VCC | V | ||
Ilkg(ERR) | ERR leakage current | V(ERR) = 5 V | 3 | µA | ||
V(IREF) | IREF voltage | R(IREF) = 20.5 kΩ | 1.204 | 1.229 | 1.254 | V |
VOH(SDO) | SDO output-high voltage | I(SDO) = –4 mA | 0.9 VCC | V | ||
VOL(SDO) | SDO output-low voltage | I(SDO) = 4 mA | 0.1 VCC | V | ||
OUTPUT STAGE (OUTx) | ||||||
I(OUTx,max) | Constant output current | V(OUTx) = 0.75 V, R(IREF) = 12.2 kΩ, Dot correction = 255 |
50 | mA | ||
V(OUTx) = 1.2 V, R(IREF) = 8.13 kΩ, Dot correction = 255 |
75 | |||||
I(OUTx,min) | Minimum current-sink capability | V(OUTx) = 0.75 V, RREF = 12.2 kΩ, dot correction = 255 |
0.15 | 0.165 | 0.18 | mA |
I(OUTx,default) | Constant output current | V(OUTx) = 0.75 V, reference fault detected, Dot correction = 255 |
7.5 | 10 | 14 | mA |
V(OUT,min) | Minimum output voltage | VCC = 3.3 V, R(IREF) = 12.2 kΩ, dot correction = 255 | 0.75 | V | ||
VCC = 5 V, R(IREF) = 12.2 kΩ, dot correction = 255 | 0.5 | |||||
VCC = 5 V, R(IREF) = 8.13 kΩ, dot correction = 255 | 1.2 | |||||
DNL | Output-current dot-correction differential nonlinearity | VCC = 5 V, R(IREF) = 12.2 kΩ, (50-mA maximum output current) | –0.6 | 0.6 | mA | |
VCC = 5 V, R(IREF) = 61 kΩ, (10-mA maximum output current) | –0.08 | 0.08 | ||||
ΔI(OUTx) | Output current absolute error percentage | V(OUTx) = 0.75 V, R(IREF) = 12.2 kΩ (50 mA), dot correction = 255 | –3% | 3% | ||
V(OUTx) = 0.75 V, R(IREF) = 20.5 kΩ (30 mA), dot correction = 255 | –3% | 3% | ||||
V(OUTx) = 0.75 V, R(IREF) = 61 kΩ (10 mA), dot correction = 255 | –7.5% | 7.5% | ||||
V(OUTx) = 1.2 V, R(IREF) = 8.13 kΩ (75 mA), dot correction = 255 | –3% | 3% | ||||
ΔI(OUT_VOUT) | Output current dependency on OUTx voltage | V(OUTx) = 0.75 V, R(IREF) = 12.2 kΩ (50 mA), ΔI(OUT_VOUT) = (I(OUT_7V) – I(OUT_1V) / I(IDEAL)) × 100 | –0.5% | 0.5% | ||
K(OUT) | Ratio of output current to IREF current, K = I(OUTx) / I(IREF) | Dot correction = 255 | 500 | mA/mA | ||
Ilkg(OUTx) | Output leakage current | [CH_EN_MASKx] = 1, [DIS_OFF_FAULT_DIAG] = 1, V(OUTx) = 6.7 V, V(SENSE) = 7 V, TA = 125°C | 0.5 | µA | ||
Ilkg(SENSE) | Leakage current at SENSE pin | VCC = 0, V(SENSE) = 5 V | 10 | µA | ||
I(IREF_octh) | IREF resistor open-circuit detection threshold | VCC = 5 V | 4.5 | 15 | µA | |
I(IREF_octh,hyst) | IREF resistor open-circuit detection-threshold hysteresis | VCC = 5 V | 2 | µA | ||
I(IREF_scth) | IREF resistor short-circuit detection threshold | VCC = 5 V | 160 | 260 | µA | |
I(IREF_scth,hyst) | IREF resistor short-circuit detection-threshold hysteresis | VCC = 5 V | 20 | µA | ||
I(OUT_PULLUP) | Channel pullup current during deactivated state | VCC = 5 V, V(OUTx) = 1 V | 50 | µA | ||
PROTECTION CIRCUITS | ||||||
V(WLS) | Weak LED supply-detection threshold voltage | [WLS_TH] = 0 | 4.1 | 4.2 | 4.3 | V |
V(WLS_hyst) | Weak LED supply hysteresis | [WLS_TH] = 0 | 0.1 | V | ||
V(WLS_OPT) | Weak LED supply detection-threshold voltage | [WLS_TH] = 1 | 2.7 | 2.77 | 2.85 | V |
V(WLS_hyst_OPT) | Weak LED supply hysteresis | [WLS_TH] = 1 | 0.1 | V | ||
V(SC_th) | Short circuit-to-V(SENSE) detection threshold, voltage difference between V(SENSE) and V(OUTx) | 0.5 | 0.7 | 0.9 | V | |
V(SC_hyst) | Short circuit-to-V(SENSE) detection hysteresis | 0.1 | V | |||
V(OC_th) | Open-circuit detection threshold | 0.1 | 0.2 | 0.3 | V | |
V(OC_hyst) | Open-circuit-detection hysteresis | 0.05 | V | |||
T(TSD) | Thermal-shutdown junction temperature | 150 | 165 | ºC | ||
T(HYS) | Thermal shutdown or warning junction temperature hysteresis | 15 | ºC | |||
T(PTW) | Pre-thermal warning junction-temperature threshold | 125 | 135 | 150 | ºC |
MIN | NOM | MAX | UNIT | |||
---|---|---|---|---|---|---|
f(SCK) | Clock frequency, cascade operation | 1 | 10 | MHz | ||
tc(SCK) | SCK cycle time | 100 | ns | |||
tw(LAH), tw(WLAH) | Pulse duration, LATCH | 380 | ns | |||
tw(CKH), tw(WCKH) | SCK high pulse duration | 50 | ns | |||
tw(CKL), tw(WCKL) | SCK low pulse duration | 50 | ns | |||
tw(SEW), tw(WDI) | SDI high and low pulse duration | 150 | ns | |||
tsu(SEST) | SDI setup time prior to SCK rise | 75 | ns | |||
th(SEHD) | SDI hold time after SCK rise | 75 | ns | |||
tr | Output rise time (SCK) | 50 | ns | |||
tf | Output fall time (SCK) | 50 | ns |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
f(SCK) | Clock frequency | Cascade operation | 10 | MHz | ||
td(LAH) | Latch switching delay | 3000 | ns | |||
tpd(SOH) | SDO propagation delay time (L to H) | 1000 | ns | |||
tpd(SOL) | SDO propagation delay (H to L) | 3000 | ns | |||
tpd(LAOL) | High to low propagation delay time (LATCH – OUT) | 750 | 3000 | ns | ||
tpd(CKLAH) | Low-to-high propagation delay time (SCK – LATCH) | 200 | ns | |||
tpd(CKDOH) | Low-to-high propagation delay time (SCK – SDO) | 30 | 75 | ns | ||
tpd(CKDOHL) | High-to-low propagation delay time (SCK – SDO) | 30 | 75 | ns | ||
tr(o) | Rise time, outputs (OFF) SDO | 50 | ns | |||
tf(o) | Fall time, outputs (ON) SDO | 50 | ns | |||
td(PWM_ON) | Output delay time from PWMx to I(OUTx) | PWMx falling threshold from 0.4 VCC to I(OUTx) rising threshold 10% of I(OUTx,max) | 0.09 | 0.13 | 0.2 | µs |
td(PWM_OFF) | Output delay time PWMx to IOUTx | PWMx rising threshold from 0.4 VCC to I(OUTx) falling threshold 90% of I(OUTx,max) | 0.09 | 0.13 | 0.2 | µs |
tr | Output rise time | Default slew rate, rise time from 10% to 90% current, 30-pF loading capacitance | 0.3 | µs | ||
With slow-slew-rate register option, rise time from 10% to 90% current, 30-pF loading capacitance | 0.8 | |||||
tf | Output fall time | Default slew rate, fall time from 90% to 10% current, 30-pF loading capacitance | 0.3 | µs | ||
With slow-slew-rate register option, fall time from 90% to 10% current, 30-pF loading capacitance | 0.8 | |||||
t(DEG) | Output open or short degllitch time | 1 | 2 | 3 | µs | |
t(REF_DEG) | Reference open or short deglitch time | 100 | µs | |||
t(PWM) | PWM edge detection timer | Timer length for PWM edge detection | 17 | 20 | 23 | ms |
VCC = 3.3 V | R(IREF) = 12.2 kΩ | TA = 25ºC |
Dot correction = 255 |
VCC = 5.5 V | TA = 25ºC | Dot correction = 255 |
VCC = 5.5 V | TA = 125ºC | Dot correction = 255 |
VCC = 5.5 V | TA = 25ºC | Dot correction = 255 |
VCC = 5.5 V | VO = 0.7 V | Dot correction = 255 |
TA = 25ºC |
VO = 0.7 V | IO = 51.4 mA | |
VCC = 5.5 V | TA = 25ºC | R(IREF) = 12.2 kΩ |
Dot correction = 255 |
VCC = 5.5 V | TA = –40ºC | Dot correction = 255 |
VCC = 5.5 V | Channel = IOUT5 | Dot correction = 255 |
VCC = 5.5 V | TA = 25ºC | Dot correction = 255 |
VO = 0.7 V | TA = 25ºC | Dot correction = 255 |
VO = 0.7 V | TA = 25ºC | |