SLVSEB5A July   2018  – August 2018 TLC6C5716-Q1

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Typical Application Schematic
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Switching Characteristics
    8. 6.8 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Maximum Constant-Sink-Current Setting
      2. 7.3.2 Brightness Control and Dot Correction
      3. 7.3.3 Grayscale Configuration
        1. 7.3.3.1 PWM Auto Repeat
        2. 7.3.3.2 PWM Timing Reset
      4. 7.3.4 Diagnostics
        1. 7.3.4.1  LED Diagnostics
        2. 7.3.4.2  Adjacent-Pin-Short Check
        3. 7.3.4.3  IREF-Short and IREF-Open Detection
        4. 7.3.4.4  Pre-Thermal Warning Flag
        5. 7.3.4.5  Thermal Error Flag
        6. 7.3.4.6  Negate-Bit Toggle
        7. 7.3.4.7  LOD_LSD Self-Test
        8. 7.3.4.8  ERR Pin
        9. 7.3.4.9  ERROR Clear
        10. 7.3.4.10 Global Reset
        11. 7.3.4.11 Slew Rate Control
        12. 7.3.4.12 Channel Group Delay
    4. 7.4 Device Functional Modes
      1. 7.4.1 Power Up
      2. 7.4.2 Device Initialization
      3. 7.4.3 Fault Mode
      4. 7.4.4 Normal Operation
    5. 7.5 Programming
      1. 7.5.1 Register Write and Read
        1. 7.5.1.1 FC-BC-DC Write
          1. 7.5.1.1.1 FC Data Write
          2. 7.5.1.1.2 BC Data Write
          3. 7.5.1.1.3 DC Data Write
        2. 7.5.1.2 Grayscale Data Write
        3. 7.5.1.3 Special Command Function
          1. 7.5.1.3.1 GS Read
          2. 7.5.1.3.2 FC-BC-DC Read
          3. 7.5.1.3.3 Status Information Data Read
    6. 7.6 Register Maps
      1. 7.6.1 GRAYSCALE Registers
        1. 7.6.1.1 OUTn_GS Register (Offset = 0h)
          1. Table 25. OUTn_GS Register Field Descriptions
      2. 7.6.2 FC-BC-DC Registers
        1. 7.6.2.1 FC-BC-DC Register (Offset = 1h)
          1. Table 28. FC-BC-DC Register Field Descriptions
      3. 7.6.3 SID Registers
        1. 7.6.3.1 SID Register (Offset = 2h)
          1. Table 31. SID Register Field Descriptions
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Receiving Notification of Documentation Updates
    2. 11.2 Community Resources
    3. 11.3 Trademarks
    4. 11.4 Electrostatic Discharge Caution
    5. 11.5 Glossary
  12. 12Mechanical, Packaging, and Orderable Information
    1. 12.1 Package Option Addendum
      1. 12.1.1 Packaging Information
      2. 12.1.2 Tape and Reel Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)

7.5.1.3.3 Status Information Data Read

Status information data (SID) is 132 bits long and contains device status information and LED fault information. Table 22 describes the bit mapping when the SID data loads into the common shift register.

Bits 287–240 are the LED-open information for the output channels, bits 203–144 are the LED-short information for the output channels, bits 239–216 are the adjacent-pin-short information for the output channels, bits 215–206 are the error status registers, bits 205–204 are the negate bits, and the others are reserved registers.

After power on, all error status registers are set to 0. If any one of the error-status-register flags (bits 215-206) asserts, the registers latch the faults until a reset error command is executed to clear the faults. But the LOD_LSD data continues to update every PWM cycle.

Table 22. SID Register

BITS OF COMMON SHIFT REGISTER DESCRIPTION
287–280 LOD2 data for OUTB7–OUTB0
279–272 Reserved
271–264 LOD2 data for OUTR7–OUTR0
263–256 LOD1 data for OUTB7–OUTB0
255–248 Reserved
247–240 LOD1 data for OUTR7–OUTR0
239–232 APS data for OUTB7–OUTB0
231–224 APS data for NU pins [pin 7, pin 10, pin 13, pin 16, pin 23, pin 26, pin 29, pin 32]
223–216 APS data for OUTR7–OUTR0
215 Thermal error flag (TEF). 0b = Normal temperature condition, 1b = High-temperature condition.
214 Pre-thermal warning (PTW). 0b = No pre-thermal warning, 1b = Pre-thermal threshold triggered.
213–211 Adjacent-pin short-check result (APS_FLAG). 011b: pass, 110b: fail.
210 IREF-resistor short flag (ISF). 0b = IREF resistor is not shorted, 1b = IREF resistor short detected.
209 IREF-resistor open flag (IOF). 0b = IREF Resistor is not open, 1b = IREF resistor open detected.
208–206 LOD-LSD detection circuit self-test result (LOD_LSD_FLAG). 011b: pass, 110b: fail.
205 Negate bit for LOD1-LSD1 register (NEG1)
204 Negate bit for LOD2-LSD2 register (NEG2)
203–192 Reserved
191–184 LSD2 data for OUTB7–OUTB0
183–176 Reserved
175–168 LSD2 data for OUTR7–OUTR0
167–160 LSD1 data for OUTB7–OUTB0
159–152 Reserved
151–144 LSD1 data for OUTR7–OUTR0
143–0 Reserved