SLASEK2A December   2017  – August 2018 TLC6C5724-Q1

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Typical Application Schematic
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Switching Characteristics
    8. 6.8 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Maximum Constant-Sink-Current Setting
      2. 7.3.2 Brightness Control and Dot Correction
      3. 7.3.3 Grayscale Configuration
        1. 7.3.3.1 PWM Auto Repeat
        2. 7.3.3.2 PWM Timing Reset
      4. 7.3.4 Diagnostics
        1. 7.3.4.1  LED Diagnostics
        2. 7.3.4.2  Adjacent-Pin-Short Check
        3. 7.3.4.3  IREF Short and IREF Open Detection
        4. 7.3.4.4  Pre-Thermal Warning Flag
        5. 7.3.4.5  Thermal Error Flag
        6. 7.3.4.6  Negate Bit Toggle
        7. 7.3.4.7  LOD_LSD Self-Test
        8. 7.3.4.8  ERR Pin
        9. 7.3.4.9  ERROR Clear
        10. 7.3.4.10 Global Reset
        11. 7.3.4.11 Slew Rate Control
        12. 7.3.4.12 Channel Group Delay
    4. 7.4 Device Functional Modes
      1. 7.4.1 Power Up
      2. 7.4.2 Device Initialization
      3. 7.4.3 Fault Mode
      4. 7.4.4 Normal Operation
    5. 7.5 Programming
      1. 7.5.1 Register Write and Read
        1. 7.5.1.1 FC-BC-DC Write
          1. 7.5.1.1.1 FC Data Write
          2. 7.5.1.1.2 BC Data Write
          3. 7.5.1.1.3 DC Data Write
        2. 7.5.1.2 Grayscale Data Write
        3. 7.5.1.3 Special Command Function
          1. 7.5.1.3.1 GS Read
          2. 7.5.1.3.2 FC-BC-DC Read
          3. 7.5.1.3.3 Status Information Data Read
    6. 7.6 Register Maps
      1. 7.6.1 GRAYSCALE Registers
        1. 7.6.1.1 OUTn_GS Register (Offset = 0h)
          1. Table 25. OUTn_GS Register Field Descriptions
      2. 7.6.2 FC-BC-DC Registers
        1. 7.6.2.1 FC-BC-DC Register (Offset = 1h)
          1. Table 28. FC-BC-DC Register Field Descriptions
      3. 7.6.3 SID Registers
        1. 7.6.3.1 SID Register (Offset = 2h)
          1. Table 31. SID Register Field Descriptions
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Receiving Notification of Documentation Updates
    2. 11.2 Community Resources
    3. 11.3 Trademarks
    4. 11.4 Electrostatic Discharge Caution
    5. 11.5 Glossary
  12. 12Mechanical, Packaging, and Orderable Information
    1. 12.1 Package Option Addendum
      1. 12.1.1 Packaging Information
      2. 12.1.2 Tape and Reel Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)

7.3.4.2 Adjacent-Pin-Short Check

The device implements the APS check function to detect the adjacent-pin short failures during system initialization. TI recommends to do an APS check when channels are all off. The APS check can be executed by writing the APS check command.

If there is no adjacent-pin short failure, the device passes the APS check and 011b is latched into APS FLAG in the error status register. The 24-bit APS register is 0. If there are two adjacent pins shorted, 110b is latched into APS_FLAG in the error status register. The corresponding bit in the APS register is set to 1. Users can read out the 24-bit data from the APS register to check which channel has the APS failure. Table 7 shows the details of the APS_FLAG and APS register. Table 8 shows the bit arrangement of the APS register. To read this APS information, see Table 22.

Table 7. APS Flag and APS Register

REGISTER VALUE DESCRIPTION
APS_FLAG 011b Pass, no adjacent pins short
110b Fail, adjacent pins short
Bit in APS register (24-bit total) 0b This OUTn pin is not shorted with other pins
1b This OUTn pin is shorted with other pins

Table 8. Bit Arrangement of the APS Register

BIT OF APS REGISTERS CORRESPONDING OUTPUTS
Bit 23 OUTB7
Bit 22 OUTB6
Bit 21 OUTB5
Bit 20 OUTB4
Bit 19 OUTB3
Bit 18 OUTB2
Bit 17 OUTB1
Bit 16 OUTB0
Bit 15 OUTG7
Bit 14 OUTG6
Bit 13 OUTG5
Bit 12 OUTG4
Bit 11 OUTG3
Bit 10 OUTG2
Bit 9 OUTG1
Bit 8 OUTG0
Bit 7 OUTR7
Bit 6 OUTR6
Bit 5 OUTR5
Bit 4 OUTR4
Bit 3 OUTR3
Bit 2 OUTR2
Bit 1 OUTR1
Bit 0 OUTR0

APS_FLAG and the APS registers are all 0 by default. After an APS check command, APS_FLAG should be 011b or 110b. Otherwise there is a failure in the APS check circuit. If the APS check result fails, the ERR pin is pulled low, the APS_FLAG value is 110b, and the ERR pin status stays unchanged until the fault is removed and the user executes an ERROR clear command. Figure 5 and Figure 9 show more detail.

As different LEDs have different parasitic capacitance, to make sure the APS Check function is suitable for all kinds of LEDs, the device provides two configuration bits for APS current and APS time. The APS current is selected by APS_CURRENT as shown in Table 9. The APS time is selected by APS_TIME as shown in Table 10.

Table 9. APS Current Selection

APS_CURRENT BIT APS CURRENT
0b 20 µA
1b 40 µA

Table 10. APS Time Selection

APS_TIME BIT ADJACENT-PIN-SHORT DETECTION TIME
0b 10 µs
1b 20 µs