SLASEJ5B October 2017 – January 2020 TLC6C5816-Q1
PRODUCTION DATA.
The TLC6C5816-Q1 device contains a 24-bit shift-register serial interface that feeds a 24-bit D-type storage register. Data transfer through the shift and storage registers is on the rising edge of the shift register clock (SRCK) and register latch signal (RCK), respectively. The storage register transfers data to the output buffer when device enable (EN) is low and shift register clear (CLR) is high.