SLIS141C December   2012  – July 2016 TLC6C5912-Q1

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Characteristics
    7. 6.7 Typical Characteristics
  7. 7 Parameter Measurement Information
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Thermal Shutdown
      2. 8.3.2 Serial-In Interface
      3. 8.3.3 Clear Register
      4. 8.3.4 Cascade Through SER OUT
      5. 8.3.5 Output Control
    4. 8.4 Device Functional Modes
      1. 8.4.1 Operation With VCC < 3 V
      2. 8.4.2 Operation With 5.5 V ≤ VCC ≤ 8 V
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curve
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Receiving Notification of Documentation Updates
    2. 12.2 Community Resources
    3. 12.3 Trademarks
    4. 12.4 Electrostatic Discharge Caution
    5. 12.5 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5 Pin Configuration and Functions

PW Package
20-Pin TSSOP
Top View
DW Package
20-Pin SOIC
Top View

Pin Functions

PIN I/O DESCRIPTION
NAME NO.
CLR 9 I Shift register clear, active-low: CLR is the signal used to clear all the registers. The storage register transfers data to the output buffer when shift register clear CLR is high. Driving CLR is low clears all the registers in the device.
DRAIN0 3 O Open-drain output: DRAIN0 to DRAIN11 are the LED current-sink channels. These pins connect to the LED cathodes, and they can survive up to 40-V LED supply voltage. This is quite helpful during automotive load-dump conditions.
DRAIN1 4 O
DRAIN2 5 O
DRAIN3 6 O
DRAIN4 7 O
DRAIN5 8 O
DRAIN6 13 O
DRAIN7 14 O
DRAIN8 15 O
DRAIN9 16 O
DRAIN10 17 O
DRAIN11 18 O
G 10 I

Output enable, active-low: G is the LED channel enable and disable input pin. Having G low enables all drain channels according to the output-latch register content. When high, all channels are off.
GND 20 —

Power ground: GND is the ground reference pin for the device. This pin must connect to the ground plane on the PCB.
RCK 12 I Register clock: RCK is the storage register clock. The data in each shift register stage transfers to the storage register at the rising edge of RCK. Data in the storage register appears at the output whenever the output enable G̅ input signal is high.
SER IN 2 I Serial-data input: SER IN is the serial data input. Data on SER IN loads into the internal register on each rising edge of SRCK.
SER OUT 11 O Serial-data output: SER OUT is the serial data output of the 12−bit serial shift register. The purpose of this pin is to cascade several devices on the serial bus. By connecting the SER OUT pin to the SER IN input of the next device on the serial bus to cascade, the data transfers to the next device on the falling edge of SRCK. This can improve the cascade application reliability, as it can avoid the issue that the second device receives SRCK and data input at the same rising edge of SRCK.
SRCK 19 I Shift-register clock: SRCK is the serial clock input. On each rising SRCK edge, data transfers from SER IN to the internal serial shift registers.
VCC 1 I Power supply: VCC is the power supply pin voltage for the device. TI recommends adding a 0.1 μF ceramic capacitor close to the pin.