The TLC6C598-Q1 is a monolithic, medium-voltage, low-current power 8-bit shift register designed for use in systems that require relatively moderate load power, such as LEDs.
This device contains an 8-bit serial-in, parallel-out shift register that feeds an 8-bit D-type storage register. Data transfers through both the shift and storage registers on the rising edge of the shift-register clock (SRCK) and the register clock (RCK), respectively. The storage register transfers data to the output buffer when shift register clear (CLR) is high. A low on CLR clears all registers in the device. Holding the output enable (G) high, holds all data in the output buffers low, and all drain outputs are off. Holding G low makes data from the storage register transparent to the output buffers. When data in the output buffers is low, the DMOS transistor outputs are off. When data is high, the DMOS transistor outputs have sink-current capability. The serial output (SER OUT) clocks out of the device on the falling edge of SRCK to provide additional hold time for cascaded applications. This provides improved performance for applications where clock signals may be skewed, devices are not located near one another, or the system must tolerate electromagnetic interference. The device contains built-in thermal shutdown protection.
Outputs are low-side, open-drain DMOS transistors with output ratings of 40 V and 50 mA continuous sink-current capabilities when Vcc = 5 V. The current limit decreases as the junction temperature increases for additional device protection. The device also provides up to 2000 V of ESD protection when tested using the human-body model and 200 V when using the machine model.
The TLC6C598-Q1 characterization is for for operation over the operating ambient temperature range of −40°C to 125°C.
PART NUMBER | PACKAGE | BODY SIZE (NOM) |
---|---|---|
TLC6C598-Q1 | SOIC (16) | 9.90 mm x 3.91 mm |
TSSOP (16) | 5.00 mm x 4.40 mm |
Changes from C Revision (October 2015) to D Revision
Changes from B Revision (March 2013) to C Revision
PIN | I/O | DESCRIPTION | |
---|---|---|---|
NAME | NO. | ||
CLR | 7 | I | Shift register clear, active-low. The storage register transfers data to the output buffer when CLR is high. Driving CLR low clears all the registers in the device. |
DRAIN0 | 3 | O | Open-drain output, LED current-sink channel, connect to LED cathode |
DRAIN1 | 4 | O | Open-drain output, LED current-sink channel, connect to LED cathode |
DRAIN2 | 5 | O | Open-drain output, LED current-sink channel, connect to LED cathode |
DRAIN3 | 6 | O | Open-drain output, LED current-sink channel, connect to LED cathode |
DRAIN4 | 11 | O | Open-drain output, LED current-sink channel, connect to LED cathode |
DRAIN5 | 12 | O | Open-drain output, LED current-sink channel, connect to LED cathode |
DRAIN6 | 13 | O | Open-drain output, LED current-sink channel, connect to LED cathode |
DRAIN7 | 14 | O | Open-drain output, LED current-sink channel, connect to LED cathode |
G | 8 | I | Output enable, active-low. LED-channel enable and disable input pin. Having G low enables all drain channels according to the output-latch register content. When high, all channels are off. |
GND | 16 | — | Power ground, the ground reference pin for the device. This pin must connect to the ground plane on the PCB. |
RCK | 10 | I | Register clock. The data in each shift register stage transfers to the storage register at the rising edge of RCK. |
SER IN | 2 | I | Serial data input. Data on SER IN loads into the internal register on each rising edge of SRCK. |
SER OUT | 9 | O | Serial data output of the 8-bit serial shift register. The purpose of this pin is to cascade several devices on the serial bus. |
SRCK | 15 | I | Serial clock input. On each rising SRCK edge, data transfers from SER IN to the internal serial shift registers. |
VCC | 1 | I | Power supply pin for the device. TI recommends adding a 0.1-μF ceramic capacitor close to the pin. |