The TLC6C598-Q1 is a monolithic, medium-voltage, low-current power 8-bit shift register designed for use in systems that require relatively moderate load power, such as LEDs.
This device contains an 8-bit serial-in, parallel-out shift register that feeds an 8-bit D-type storage register. Data transfers through both the shift and storage registers on the rising edge of the shift-register clock (SRCK) and the register clock (RCK), respectively. The storage register transfers data to the output buffer when shift register clear (CLR) is high. A low on CLR clears all registers in the device. Holding the output enable (G) high, holds all data in the output buffers low, and all drain outputs are off. Holding G low makes data from the storage register transparent to the output buffers. When data in the output buffers is low, the DMOS transistor outputs are off. When data is high, the DMOS transistor outputs have sink-current capability. The serial output (SER OUT) clocks out of the device on the falling edge of SRCK to provide additional hold time for cascaded applications. This provides improved performance for applications where clock signals may be skewed, devices are not located near one another, or the system must tolerate electromagnetic interference. The device contains built-in thermal shutdown protection.
Outputs are low-side, open-drain DMOS transistors with output ratings of 40 V and 50 mA continuous sink-current capabilities when Vcc = 5 V. The current limit decreases as the junction temperature increases for additional device protection. The device also provides up to 2000 V of ESD protection when tested using the human-body model and 200 V when using the machine model.
The TLC6C598-Q1 characterization is for for operation over the operating ambient temperature range of −40°C to 125°C.
PART NUMBER | PACKAGE | BODY SIZE (NOM) |
---|---|---|
TLC6C598-Q1 | SOIC (16) | 9.90 mm x 3.91 mm |
TSSOP (16) | 5.00 mm x 4.40 mm |
Changes from C Revision (October 2015) to D Revision
Changes from B Revision (March 2013) to C Revision
PIN | I/O | DESCRIPTION | |
---|---|---|---|
NAME | NO. | ||
CLR | 7 | I | Shift register clear, active-low. The storage register transfers data to the output buffer when CLR is high. Driving CLR low clears all the registers in the device. |
DRAIN0 | 3 | O | Open-drain output, LED current-sink channel, connect to LED cathode |
DRAIN1 | 4 | O | Open-drain output, LED current-sink channel, connect to LED cathode |
DRAIN2 | 5 | O | Open-drain output, LED current-sink channel, connect to LED cathode |
DRAIN3 | 6 | O | Open-drain output, LED current-sink channel, connect to LED cathode |
DRAIN4 | 11 | O | Open-drain output, LED current-sink channel, connect to LED cathode |
DRAIN5 | 12 | O | Open-drain output, LED current-sink channel, connect to LED cathode |
DRAIN6 | 13 | O | Open-drain output, LED current-sink channel, connect to LED cathode |
DRAIN7 | 14 | O | Open-drain output, LED current-sink channel, connect to LED cathode |
G | 8 | I | Output enable, active-low. LED-channel enable and disable input pin. Having G low enables all drain channels according to the output-latch register content. When high, all channels are off. |
GND | 16 | — | Power ground, the ground reference pin for the device. This pin must connect to the ground plane on the PCB. |
RCK | 10 | I | Register clock. The data in each shift register stage transfers to the storage register at the rising edge of RCK. |
SER IN | 2 | I | Serial data input. Data on SER IN loads into the internal register on each rising edge of SRCK. |
SER OUT | 9 | O | Serial data output of the 8-bit serial shift register. The purpose of this pin is to cascade several devices on the serial bus. |
SRCK | 15 | I | Serial clock input. On each rising SRCK edge, data transfers from SER IN to the internal serial shift registers. |
VCC | 1 | I | Power supply pin for the device. TI recommends adding a 0.1-μF ceramic capacitor close to the pin. |
MIN | MAX | UNIT | ||
---|---|---|---|---|
VCC | Logic supply voltage | –0.3 | 8 | V |
VI | Logic input-voltage range | –0.3 | 8 | V |
VDS | Power DMOS drain-to-source voltage | –0.3 | 42 | V |
Continuous total dissipation | See Thermal Information | |||
TA | Operating ambient temperature | –40 | 125 | °C |
TJ | Operating junction temperature range | –40 | 150 | °C |
Tstg | Storage temperature range | –55 | 165 | °C |
VALUE | UNIT | ||||
---|---|---|---|---|---|
V(ESD) | Electrostatic discharge | Human body model (HBM), per AEC Q100-002(1) | ±2000 | V | |
Charged device model (CDM), per AEC Q100-011 | All pins | ±750 | |||
Corner pins (1, 8, 9, and 16) | ±750 |
MIN | MAX | UNIT | ||
---|---|---|---|---|
VCC | Supply voltage | 3 | 5.5 | V |
VIH | High-level input voltage | 2.4 | V | |
VIL | Low-level input voltage | 0.7 | V | |
TA | Operating ambient temperature | –40 | 125 | °C |
THERMAL METRIC(1) | TLC6C598-Q1 | UNIT | ||
---|---|---|---|---|
PW (TSSOP) | D (SOIC) | |||
16 PINS | 16 PINS | |||
RθJA | Junction-to-ambient thermal resistance | 129.4 | 100 | °C/W |
RθJC(top) | Junction-to-case (top) thermal resistance | 55.4 | 45 | °C/W |
RθJB | Junction-to-board thermal resistance | 65.8 | 40 | °C/W |
ψJT | Junction-to-top characterization parameter | 9.9 | 10 | °C/W |
ψJB | Junction-to-board characterization parameter | 65.2 | 40 | °C/W |
RθJC(bot) | Junction-to-case (bottom) thermal resistance | NA | NA | °C/W |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | ||
---|---|---|---|---|---|---|---|
DRAIN0 to DRAIN7. Drain-to-source voltage | 40 | V | |||||
VOH | High-level output voltage, SER OUT | IOH = –20 μA | VCC = 5 V | 4.9 | 4.99 | V | |
IOH = −4 mA | 4.5 | 4.69 | V | ||||
VOL | Low-level output voltage, SER OUT | IOH = 20 μA | VCC = 5 V | 0.001 | 0.01 | V | |
IOH = 4 mA | 0.25 | 0.4 | V | ||||
IIH | High-level input current | VCC = 5 V, VI = VCC | 0.2 | μA | |||
IIL | Low-level input current | VCC = 5 V, VI = 0 | –0.2 | μA | |||
ICC | Logic supply current | VCC = 5 V, no clock signal | All outputs off | 0.1 | 1 | μA | |
All outputs on | 88 | 160 | |||||
ICC(FRQ) | Logic supply current at frequency | fSRCK = 5 MHz, CL = 30 pF | All outputs on | 200 | μA | ||
IDSX | Off-state drain current | VDS = 30 V | VCC = 5 V | 0.1 | μA | ||
VDS = 30 V, TC = 125°C | VCC = 5 V | 0.15 | 0.3 | ||||
rDS(on) | Static drain-source on-state resistance | ID = 20 mA, VCC = 5 V, TA = 25°C, Single channel ON |
6 | 7.41 | 8.6 | Ω | |
ID = 20 mA, VCC = 5 V, TA = 25°C, All channels ON |
6.7 | 8.3 | 9.6 | ||||
ID = 20 mA, VCC = 3.3 V, TA = 25°C, Single channel ON |
7.9 | 9.34 | 11.2 | ||||
ID = 20 mA, VCC = 3.3 V, TA = 25°C, All channels ON |
8.7 | 10.25 | 12.3 | ||||
ID = 20 mA, VCC = 5 V, TA = 125°C, Single channel ON |
9.1 | 11.13 | 12.9 | ||||
ID = 20 mA, VCC = 5 V, TA = 125°C, All channels ON |
10.3 | 12.28 | 14.5 | ||||
ID = 20 mA, VCC = 3.3 V, TA = 125°C, Single channel ON |
11.6 | 13.69 | 16.4 | ||||
ID = 20 mA, VCC = 3.3 V, TA = 125°C, All channels ON |
12.8 | 14.89 | 18.2 | ||||
TSHUTDOWN | Thermal shutdown trip point | 150 | 175 | 200 | ºC | ||
Thys | Hysteresis | 15 | ºC |
MIN | NOM | MAX | UNIT | ||
---|---|---|---|---|---|
tsu | Setup time, SER IN high before SRCK↑ | 15 | ns | ||
th | Hold time, SER IN high after SRCK↑ | 15 | ns | ||
tw | SER IN pulse duration | 40 | ns |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
tPLH | Propagation delay time, low-to-high-level output from G | CL = 30 pF, ID = 48 mA | 220 | ns | ||
tPHL | Propagation delay time, high-to-low-level output from G | 75 | ns | |||
tr | Rise time, drain output | 210 | ns | |||
tf | Fall time, drain output | 128 | ns | |||
tpd | Propagation delay time, SRCK↓ to SER OUT | CL = 30 pF, ID = 48 mA | 49.4 | ns | ||
tor | SER OUT rise time (10% to 90%) | CL = 30 pF | 20 | ns | ||
tof | SER OUT fall time (90% to 10%) | CL = 30 pF | 20 | ns | ||
f(SRCK) | Serial clock frequency | CL = 30 pF, ID = 20 mA | 10 | MHz | ||
tSRCK_WH | SRCK pulse duration, high | 30 | ns | |||
tSRCK_WL | SRCK pulse duration, low | 30 | ns |
Figure 1 shows the SER IN to SER OUT waveform. The output signal appears on the falling edge of the shift register clock (SRCK) because there is a phase inverter at SER OUT (see Figure 13). As a result, it takes seven and a half periods of SRCK for data to transfer from SER IN to SER OUT.
Figure 2 shows the switching times and voltage waveforms. Tests for all these parameters took place using the test circuit shown in Figure 11.
Figure 11 and Figure 12 show the resistive-load test circuit and voltage waveforms. One can see from Figure 12 that with G held low and CLR held high, the status of each drain changes on the rising edge of the register clock, indicating the transfer of data to the output buffers at that time.
The TLC6C598-Q1 device is a monolithic, medium-voltage, low-current 8-bit shift register designed to drive relatively moderate load power such LEDs. The device contains an 8-bit serial-in, parallel-out shift register that feeds an 8-bit D-type storage register. Thermal shutdown protection is also built-into the device.
The device implements an internal thermal shutdown to protect itself if the junction temperature exceeds 175°C (typical). The thermal shutdown forces the device to have an open state when the junction temperature exceeds the thermal trip threshold. Once the junction temperature decreases below 160°C (typical), the device begins to operate again.
The TLC6C598-Q1 device contains an 8-bit serial-in, parallel-out shift register that feeds an 8-bit D-type storage register. Data transfer through the shift and storage registers is on the rising edge of the shift register clock (SRCK) and the register clock (RCK), respectively. The storage register transfers data to the output buffer when shift register clear (CLR) is high.
A logic low the CLR pin clears all registers in the device. TI suggests clearing the device during power up or initialization.
DRAIN0–DRAIN7. These pins can survive up to 40-V LED supply voltage. This is quite helpful during automotive load-dump conditions.
RCK is the storage-register clock. Data in the storage register appears at the output whenever the output enable (G) input signal is high.
By connecting the SER OUT pin to the SER IN input of the next device on the serial bus to cascade, the data transfers to the next device on the falling edge of SRCK. This can improve the cascade application reliability, as it can avoid the issue that the second device receives SRCK and data input at the same rising edge of SRCK.
Holding the output enable (pin G) high holds all data in the output buffers low, and all drain outputs are off. Holding G low makes data from the storage register transparent to the output buffers. When data in the output buffers is low, the DMOS transistor outputs are off. When data is high, the DMOS transistor outputs are capable of sinking current. This pin also can be used for global PWM dimming.
This device works normally within the range 3 V ≤ VCC ≤ 5.5 V. When the operating voltage is lower than 3 V, correct behavior of the device, including communication interface and current capability, is not assured.
The device works normally in this voltage range, but reliability issues may occur if the device works for a long time in this voltage range.
NOTE
Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.
The TLC6C598-Q1 device is a serial-in, parallel-out, power and logic, 8-bit shift register with low-side open-drain DMOS output ratings of 40-V and 50-mA continuous sink-current capabilities when VCC = 5 V. The device is designed to drive resistive loads and is particularly well-suited as an interface between a microcontroller and LEDs or lamps. The device also provides up to 2000 V of ESD protection when tested using the human body model and 200 V when using the machine model
Figure 14 shows a typical cascade application circuit with two TLC6C598-Q1 chips configured in cascade topology. The MCU generates all the input signals.
DESIGN PARAMETER | EXAMPLE VALUE |
---|---|
VBattery | 9 V to 40 V |
VCC_1 | 3.3 V |
I(D0), I(D1), I(D2), I(D3) , I(D4), I(D5), I(D6), I(D7) | 30 mA |
VCC_2 | 5 V |
I(D8), I(D9), I(D10), I(D11) , I(D12), I(D13), I(D14), I(D15) | 50 mA |
To begin the design process, the designer must decide on a few parameters, as follows:
With these parameters determined, the resistor in series with the LED can be calculated by using the following equation:
The TLC6C598-Q1 device is designed to operate with an input voltage supply range from 3 V to 5.5 V. This input supply should be well regulated. TI recommends placing the ceramic bypass capacitors near the VCC pin.
There are no special layout requirement for the digital signal pins. The only requirement is placing the ceramic bypass capacitors near the corresponding pin.
Maximize the copper coverage on the PCB to increase the thermal conductivity of the board. The major heat-flow path from the package to the ambient is through the cooper on the PCB. Maximizing the copper coverage is extremely important when the design does not include heat sinks attached to the PCB on the other side of the package.
Add as many thermal vias as possible directly under the package ground pad to optimize the thermal conductivity of the board.
All thermal vias should be either plated shut or plugged and capped on both sides of the board to prevent solder voids. To ensure reliability and performance, the solder coverage should be at least 85%.
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These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
Orderable Device | Status (1) | Package Type | Package Drawing | Pins | Package Qty | Eco Plan (2) | Lead/Ball Finish(4) | MSL Peak Temp (3) | Op Temp (°C) | Device Marking(5)(6) |
---|---|---|---|---|---|---|---|---|---|---|
TLC6C598QPWRQ1 | ACTIVE | TSSOP | PW | 16 | 2000 | Green (RoHS & no Sb/Br) | CU NIPDAU | Level-3-260C-168 HR | -40 to 125 | 6C598 |
TLC6C598QDRQ1 | ACTIVE | SOIC | D | 16 | 2500 | Green (RoHS & no Sb/Br) | CU NIPDAU | Level-3-260C-168 HR | -40 to 125 | TLC6C598 |
TLC6C598CQDRQ1 | ACTIVE | SOIC | D | 16 | 2500 | Green (RoHS & no Sb/Br) | CU NIPDAU | Level-3-260C-168 HR | -40 to 125 | TLC6C598C |
Important Information and Disclaimer: The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. |
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Device | Package Type |
Package Drawing | Pins | SPQ | Reel Diameter (mm) |
Reel Width W1 (mm) |
A0 (mm) |
B0 (mm) |
K0 (mm) |
P1 (mm) |
W (mm) |
Pin1 Quadrant |
---|---|---|---|---|---|---|---|---|---|---|---|---|
TLC6C598QPWRQ1 | TSSOP | PW | 16 | 2000 | 330 | 12.4 | 6.9 | 5.6 | 1.6 | 8 | 12 | Q1 |
TLC6C598QDRQ1 | SOIC | D | 16 | 2500 | 330 | 16.4 | 6.5 | 10.3 | 2.1 | 8 | 16 | Q1 |
TLC6C598CQDRQ1 | SOIC | D | 16 | 2500 | 330 | 16.4 | 6.5 | 10.3 | 2.1 | 8 | 16 | Q1 |
Device | Package Type | Package Drawing | Pins | SPQ | Length (mm) | Width (mm) | Height (mm) |
---|---|---|---|---|---|---|---|
TLC6C598QPWRQ1 | TSSOP | PW | 16 | 2000 | 367 | 367 | 38 |
TLC6C598QDRQ1 | SOIC | D | 16 | 2500 | 367 | 367 | 38 |
TLC6C598CQDRQ1 | SOIC | D | 16 | 2500 | 367 | 367 | 38 |
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