SLIS142D December   2012  – September 2016 TLC6C598-Q1

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Switching Characteristics
    8. 6.8 Timing Waveforms
    9. 6.9 Typical Characteristics
  7. 7 Parameter Measurement Information
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Thermal Shutdown
      2. 8.3.2 Serial-In Interface
      3. 8.3.3 Clear Registers
      4. 8.3.4 Output Channels
      5. 8.3.5 Register Clock
      6. 8.3.6 Cascade Through SER OUT
      7. 8.3.7 Output Control
    4. 8.4 Device Functional Modes
      1. 8.4.1 Operation With VCC < 3 V
      2. 8.4.2 Operation With 5.5 V ≤ VCC ≤ 8 V
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curve
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Receiving Notification of Documentation Updates
    2. 12.2 Community Resources
    3. 12.3 Trademarks
    4. 12.4 Electrostatic Discharge Caution
    5. 12.5 Glossary
  13. 13Mechanical, Packaging, and Orderable Information
    1. 13.1 Package Option Addendum
      1. 13.1.1 Packaging Information
      2. 13.1.2 Tape and Reel Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)

5 Pin Configuration and Functions

PW Package
16-Pin TSSOP
Top View
D Package
16-Pin SOIC
Top View

Pin Functions

PIN I/O DESCRIPTION
NAME NO.
CLR 7 I Shift register clear, active-low. The storage register transfers data to the output buffer when CLR is high. Driving CLR low clears all the registers in the device.
DRAIN0 3 O Open-drain output, LED current-sink channel, connect to LED cathode
DRAIN1 4 O Open-drain output, LED current-sink channel, connect to LED cathode
DRAIN2 5 O Open-drain output, LED current-sink channel, connect to LED cathode
DRAIN3 6 O Open-drain output, LED current-sink channel, connect to LED cathode
DRAIN4 11 O Open-drain output, LED current-sink channel, connect to LED cathode
DRAIN5 12 O Open-drain output, LED current-sink channel, connect to LED cathode
DRAIN6 13 O Open-drain output, LED current-sink channel, connect to LED cathode
DRAIN7 14 O Open-drain output, LED current-sink channel, connect to LED cathode
G 8 I Output enable, active-low. LED-channel enable and disable input pin. Having G low enables all drain channels according to the output-latch register content. When high, all channels are off.
GND 16 — Power ground, the ground reference pin for the device. This pin must connect to the ground plane on the PCB.
RCK 10 I Register clock. The data in each shift register stage transfers to the storage register at the rising edge of RCK.
SER IN 2 I Serial data input. Data on SER IN loads into the internal register on each rising edge of SRCK.
SER OUT 9 O Serial data output of the 8-bit serial shift register. The purpose of this pin is to cascade several devices on the serial bus.
SRCK 15 I Serial clock input. On each rising SRCK edge, data transfers from SER IN to the internal serial shift registers.
VCC 1 I Power supply pin for the device. TI recommends adding a 0.1-μF ceramic capacitor close to the pin.