SLVS647I August   2006  – November 2014 TLE4275-Q1

UNLESS OTHERWISE NOTED, this document contains PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Characteristics
    7. 6.7 Typical Characteristics
  7. 7 Parameter Measurement Information
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Regulated Output (OUT)
      2. 8.3.2 Power-On-Reset (RESET)
      3. 8.3.3 Reset Delay Timer (DELAY)
    4. 8.4 Device Functional Modes
      1. 8.4.1 Low-Voltage Tracking
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Power-Up Reset Capacitance
        2. 9.2.2.2 Thermal Consideration
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 Trademarks
    3. 12.3 Electrostatic Discharge Caution
    4. 12.4 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • KTT|5
  • PWP|20
  • KVU|5
Thermal pad, mechanical data (Package|Pins)
Orderable Information

9 Application and Implementation

NOTE

Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.

9.1 Application Information

Figure 19 shows typical application circuits for the TLE4275-Q1. Based on the end-application, different values of external components can be used. An application can require a larger output capacitor during fast load steps in order to prevent a reset from occurring. TI recommends a low-ESR ceramic capacitor with a dielectric of type X5R or X7R for better load transient response.

9.2 Typical Application

TLE4275-Q1 data_1_SLVS647.gifFigure 19. Typical Application Diagram

9.2.1 Design Requirements

For this design example, use the parameters listed in Table 1.

Table 1. Design Parameters

DESIGN PARAMETER EXAMPLE VALUE
Input voltage range 4 to 40 V
Output voltage 5 V
Output current rating 400 mA
Output capacitor range 10 to 500 µF
Output capacitor ESR range 1 mΩ to 20 Ω
DELAY capacitor range 100 pF to 500 nF

9.2.2 Detailed Design Procedure

To begin the design process, determine the following:

  • Input voltage range
  • Output voltage
  • Output current rating
  • Output capacitor
  • Power-up reset delay time

9.2.2.1 Power-Up Reset Capacitance

To calculate the power-up reset capacitance, use Equation 2.

Equation 2. TLE4275-Q1 Eq02_td2_slvs647.gif

9.2.2.2 Thermal Consideration

Calculate the power dissipated by the device according to Equation 3.

Equation 3. PT = IO × (VI – VO) + VI × IQ

where

  • PT = Total power dissipation of the device.
  • IO = output current
  • VI = input voltage
  • VO = output voltage

After determining the power dissipated by the device, calculate the junction temperature from the ambient temperature and the device thermal impedance.

Equation 4. TJ = TA + RθJA × PT

9.2.3 Application Curves

Load = 200 mA, Cin = 22 µF, Cout = 10 µF
TLE4275-Q1 scope_01_lvs647.gif
CH1：Vout, CH2: Vin, CH3: Vreset.
Figure 20. Power Up Waveform
TLE4275-Q1 scope_02_lvs647.gif
CH1：Vout, CH2: Vin, CH3: Vreset.
Figure 21. Power Down Waveform