SLLSEZ8D December 2017 – June 2022 TLIN1022-Q1
PRODUCTION DATA
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
D112V | Duty Cycle 1 (ISO/DIS 17987 Param 27)(1) | THREC(MAX) = 0.744 x VSUP, THDOM(MAX) = 0.581 x VSUP, VSUP = 7 V to 18 V, tBIT = 50 µs (20 kbps), D1 = tBUS_rec(min)/(2 x tBIT) (See Figure 7-11 and Figure 7-12) | 0.396 | |||
D112V | Duty Cycle 1 | THREC(MAX) = 0.625 x VSUP, THDOM(MAX) = 0.581 x VSUP, VSUP = 4 V to 7 V, tBIT = 50 µs (20 kbps), D1 = tBUS_rec(min)/(2 x tBIT) (See Figure 7-11 and Figure 7-12) | 0.396 | |||
D212V | Duty Cycle 2 (ISO/DIS 17987 Param 28) | THREC(MIN) = 0.422 x VSUP, THDOM(MIN) = 0.284 x VSUP, VSUP = 7.6 V to 18 V, tBIT = 50 µs (20 kbps), D2 = tBUS_rec(MAX)/(2 x tBIT) (See Figure 7-11 and Figure 7-12) | 0.581 | |||
D312V | Duty Cycle 3 (ISO/DIS 17987 Param 29) | THREC(MAX) = 0.778 x VSUP, THDOM(MAX) = 0.616 x VSUP, VSUP = 7 V to 18 V, tBIT = 96 µs (10.4 kbps), D3 = tBUS_rec(min)/(2 x tBIT) (See Figure 7-11 and Figure 7-12) | 0.417 | |||
D312V | Duty Cycle | THREC(MAX) = 0.645 x VSUP, THDOM(MAX) = 0.616 x VSUP, VSUP = 4 V to 7 V, tBIT = 96 µs (10.4 kbps), D3 = tBUS_rec(min)/(2 x tBIT) (See Figure 7-11 and Figure 7-12) | 0.417 | |||
D412V | Duty Cycle 4 (ISO/DIS 17987 Param 30) | THREC(MIN) = 0.389 x VSUP, THDOM(MIN) = 0.251 x VSUP, VSUP = 7.6 V to 18 V, tBIT = 96 µs (10.4 kbps), D4 = tBUS_rec(MAX)/(2 x tBIT) (See Figure 7-11 and Figure 7-12) | 0.59 |