SLLSFH7 August 2021 TLIN1039-Q1
PRODUCTION DATA
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
RXD Output Terminal | ||||||
VOL | Low-level voltage | Based upon external pull-up to VCC (4) | 0.6 | V | ||
IOL | Low-level output current, open drain | LIN = 0 V, RXD = 0.4 V | 1.5 | mA | ||
ILKG | Leakage current, high-level | LIN = VSUP, RXD = VCC | –5 | 5 | µA | |
TXD Input Terminal | ||||||
VIL | Low-level input voltage | 0.8 | V | |||
VIH | High-level input voltage | 2 | V | |||
ILKG | Low-level input leakage current | TXD = 0 V | –5 | 5 | µA | |
RTXD | Internal pull-down resistor value | 125 | 350 | 800 | kΩ | |
EN Input Terminal | ||||||
VIL | Low-level input voltage | –0.3 | 0.8 | V | ||
VIH | High-level input voltage | 2 | 5.25 | V | ||
VHYS | Hysteresis voltage | By design and characterization | 30 | 500 | mV | |
IIL | Low-level input current | EN = 0 V | –5 | 5 | µA | |
REN | Internal pull-down resistor | 125 | 350 | 800 | kΩ | |
LIN Terminal | ||||||
VOH | LIN recessive high-level output voltage(3) | TXD = VCC, IO = 0 mA 7 V ≤ VSUP ≤ 36 V |
0.85 | VSUP | ||
VOH | LIN recessive high-level output voltage(3) | TXD = VCC, IO = 0 mA 4.5 V ≤ VSUP < 7 V |
3 | V | ||
VOH | LIN recessive high-level output voltage(1) (2) | TXD = VCC, IO = 0 mA 7 V ≤ VSUP ≤ 18 V |
0.8 | VSUP | ||
VOL | LIN dominant low-level output voltage(3) | TXD = 0 V 7 V ≤ VSUP ≤ 36 V |
0.2 | VSUP | ||
VOL | LIN dominant low-level output voltage(3) | TXD = 0 V 4.5 V ≤ VSUP < 7 V |
1.2 | V | ||
VOL | LIN dominant low-level output voltage(1) (2) | TXD = 0 V 7 V ≤ VSUP ≤ 18 V |
0.2 | VSUP | ||
VBUSdom | Low-level input voltage ISO 17987 Param 17 |
LIN dominant (including LIN dominant for wake up) See Figure 8-3 and Figure 8-4 |
0.4 | VSUP | ||
VBUSrec | High-level input voltage ISO 17987 Param 18 |
LIN recessive See Figure 8-3 and Figure 8-4 |
0.6 | VSUP | ||
VIH | LIN recessive high-level input voltage threshold(1) (2) | 7 V ≤ VSUP ≤ 18 V | 0.47 | 0.6 | VSUP | |
VIL | LIN dominant low-level input voltage threshold(1) (2) | 7 V ≤ VSUP ≤ 18 V | 0.4 | 0.53 | VSUP | |
VSUP_NON_OP | VSUP where impact of recessive LIN bus < 5%(3) | TXD & RXD open 4.5 V ≤ LIN ≤ 45 V |
–0.3 | 42 | V | |
VBUS_CNT | Receiver center threshold | VBUS_CNT = (VBUSrec + VBUSdom)/2 See Figure 8-3 and Figure 8-4 |
0.475 | 0.5 | 0.525 | VSUP |
VHYS | Hysteresis voltage (ISO 17987) | VHYS = VBUSrec - VBUSdom
See Figure 8-3 and Figure 8-4 |
0.175 | VSUP | ||
VHYS | Hysteresis voltage (SAE J2602) | VHYS = VIH - VIL
See Figure 8-3 and Figure 8-4 |
0.07 | 0.175 | VSUP | |
VSERIAL_DIODE | Serial diode LIN termination pull-up path | ISERIAL_DIODE = 10 µA | 0.4 | 0.7 | 1.0 | V |
IBUS(LIM) | Limiting current ISO 17987 Param 12 |
TXD = 0 V, VLIN = 18 V VSUP = 18 V |
40 | 90 | 200 | mA |
IBUS_PAS_dom | Receiver leakage current, dominant | Driver off/recessive, LIN = 0 V VSUP = 12 V See Figure 8-6 |
–1 | mA | ||
IBUS_PAS_rec1 | Receiver leakage current, recessive | Driver off/recessive, LIN ≥ VSUP
4.5 V ≤ VSUP ≤ 36 V See Figure 8-7 |
20 | µA | ||
IBUS_PAS_rec2 | Receiver leakage current, recessive | Driver off/recessive, LIN = VSUP
See Figure 8-7 |
–5 | 5 | µA | |
IBUS_NO_GND | Leakage current, loss of ground | GNDDevice = VSUP = 18 V RMeas = 1 kΩ 0 V < VLIN < 18 V |
–1 | 1 | mA | |
Ileak gnd(dom) | Leakage current, loss of ground (5) | VSUP = 8 V, GND = open, VSUP = 18 V, GND = open RCOMMANDER = 1 kΩ, CL = 1 nF RRESPONDER = 20 kΩ, CL = 1 nF LIN = dominant |
–1 | 1 | mA | |
Ileak gnd(rec) | Leakage current, loss of ground (5) | VSUP = 8 V, GND = open, VSUP = 18 V, GND = open RCOMMANDER = 1 kΩ, CL = 1 nF RRESPONDER = 20 kΩ, CL = 1 nF LIN = recessive |
–100 | 100 | µA | |
IBUS_NO_BAT | Leakage current, loss of supply | VSUP = GND 0 V ≤ VLIN ≤ 18 V |
5 | µA | ||
IRSLEEP | Pull-up current source to VSUP sleep mode | VSUP = 14 V, LIN = GND | –20 | –1.5 | µA | |
RPU | Pull-up resistor to VSUP | Normal and standby modes | 20 | 45 | 60 | kΩ |
CLIN | Capacitance of the LIN pin | VSUP = 14 V | 25 | pF | ||
Duty Cycle Characteristics | ||||||
D1 | Duty Cycle 1(3)
ISO 17987 Param 27 |
THREC(MAX) = 0.744 x VSUP
THDOM(MAX) = 0.581 x VSUP VSUP = 7 V to 18 V, tBIT = 50 µs D1 = tBUS_rec(min)/(2 x tBIT) See Figure 8-10 and Figure 8-11 |
0.396 | |||
D1 | Duty Cycle 1 (3) (6) | THREC(MAX) = 0.665 x VSUP, THDOM(MAX) = 0.499 x VSUP VSUP = 4.5 V to 7 V, tBIT = 50 µs D1 = tBUS_rec(min)/(2 x tBIT) See Figure 8-10 and Figure 8-11 |
0.396 | |||
D1 | Duty cycle 1(1) (2) (6) | THREC(MAX) = 0.744 x VSUP, THDOM(MAX) = 0.581 x VSUP, VSUP = 7 V to 18 V, tBIT = 52 µs D1 = tBUS_rec(min)/(2 x tBIT) See Figure 8-10 and Figure 8-11 |
0.396 | |||
D2 | Duty Cycle 2(3)
ISO 17987 Param 28 |
THREC(MIN) = 0.422 x VSUP
THDOM(MIN) = 0.284 x VSUP VSUP = 7 V to 18 V, tBIT = 50 µs D2 = tBUS_rec(MAX)/(2 x tBIT) See Figure 8-10 and Figure 8-11 |
0.581 | |||
D2 | Duty cycle 2(3) (6) | THREC(MIN) = 0.496 x VSUP, THDOM(MIN) = 0.361 x VSUP, VSUP = 4.5 V to 7 V, tBIT = 50 µs D2 = tBUS_rec(MAX)/(2 x tBIT) See Figure 8-10 and Figure 8-11 |
0.581 | |||
D2 | Duty cycle 2(1) (2) (6) | THREC(MIN) = 0.422 x VSUP, THDOM(MIN) = 0.284 x VSUP, VSUP = 7 V to 18 V, tBIT = 52 µs D2 = tBUS_rec(MAX)/(2 x tBIT) See Figure 8-10 and Figure 8-11 |
0.581 | |||
D3 | Duty Cycle 3(3)
ISO 17987 Param 29 |
THREC(MAX) = 0.778 x VSUP
THDOM(MAX) = 0.616 x VSUP VSUP = 7 V to 18 V, tBIT = 96 µs D3 = tBUS_rec(min)/(2 x tBIT) See Figure 8-10 and Figure 8-11 |
0.417 | |||
D3 | Duty Cycle 3(3) (6) | THREC(MAX) = 0.665 x VSUP
THDOM(MAX) = 0.499 x VSUP VSUP = 4.5 V to 7 V, tBIT = 96 µs D3 = tBUS_rec(min)/(2 x tBIT) See Figure 8-10 and Figure 8-11 |
0.417 | |||
D3 | Duty cycle 3(1) (2) (6) | THREC(MAX) = 0.778 x VSUP
THDOM(MAX) = 0.616 x VSUP VSUP = 7 V to 18 V, tBIT = 96 µs D3 = tBUS_rec(min)/(2 x tBIT) See Figure 8-10 and Figure 8-11 |
0.417 | |||
D4 | Duty Cycle 4(3)
ISO 17987 Param 30 |
THREC(MIN) = 0.389 x VSUP
THDOM(MIN) = 0.251 x VSUP VSUP = 7 V to 18 V, tBIT = 96 µs D4 = tBUS_rec(MAX)/(2 x tBIT) See Figure 8-10 and Figure 8-11 |
0.59 | |||
D4 | Duty Cycle 4(3) (6) | THREC(MAX) = 0.496 x VSUP
THDOM(MAX) = 0.361 x VSUP VSUP = 4.5 V to 7 V, tBIT = 96 µs D4 = tBUS_rec(MAX)/(2 x tBIT) See Figure 8-10 and Figure 8-11 |
0.59 | |||
D4 | Duty cycle 4(1) (2) (6) | THREC(MIN) = 0.389 x VSUP
THDOM(MIN) = 0.251 x VSUP VSUP = 7 V to 18 V, tBIT = 96 µs D4 = tBUS_rec(MAX)/(2 x tBIT) See Figure 8-10 and Figure 8-11 |
0.59 | |||
D1LB | Duty cycle 1 at low battery(1) (2) (6) | THREC(MAX) = 0.665 x VSUP, THDOM(MAX) = 0.499 x VSUP, VSUP = 5.5 V to 7 V, tBIT = 52 µs |
0.396 | |||
D2LB | Duty cycle 2 at low battery(1) (2) (6) | THREC(MAX) = 0.496 x VSUP
THDOM(MAX) = 0.361 x VSUP VSUP = 6.1 V to 7 V, tBIT = 52 µs |
0.581 | |||
D3LB | Duty cycle 3 at low battery(1) (2) (6) | THREC(MAX) = 0.665 x VSUP, THDOM(MAX) = 0.499 x VSUP, VSUP = 5.5 V to 7 V, tBIT = 96 µs |
0.396 | |||
D4LB | Duty cycle 4 at low battery(1) (2) (6) | THREC(MAX) = 0.496 x VSUP
THDOM(MAX) = 0.361 x VSUP VSUP = 6.1 V to 7 V, tBIT = 96 µs |
0.581 | |||
Tr-d max_D1 | Transmitter propagation delay timings for the duty cycle(1)
(2)
(6) Recessive to dominant |
THREC(MAX) = 0.744 x VSUP, THDOM(MAX) = 0.581 x VSUP 7 V ≤ VSUP ≤ 18 V, tBIT = 52 µs tREC(MAX)_D1 - tDOM(MIN)_D1 |
10.8 | µs | ||
Td-r max_D2 | Transmitter propagation delay timings for the duty cycle(1)
(2)
(6) Dominant to recessive |
THREC(MAX) = 0.422 x VSUP, THDOM(MAX) = 0.284 x VSUP 7 V ≤ VSUP ≤ 18 V, tBIT = 52 µs tDOM(MAX)_D2 - tREC(MIN)_D2 |
8.4 | µs | ||
Tr-d max_D3 | Transmitter propagation delay timings for the duty cycle(1)
(2)
(6) Recessive to dominant |
THREC(MAX) = 0.778 x VSUP
THDOM(MAX) = 0.616 x VSUP 7 V ≤ VSUP ≤ 18 V, tBIT = 96 µs tREC(MAX)_D3 - tDOM(MIN)_D3 |
15.9 | µs | ||
Td-r max_D4 | Transmitter propagation delay timings for the duty cycle(1)
(2)
(6) Dominant to recessive |
THREC(MIN) = 0.389 x VSUP
THDOM(MIN) = 0.251 x VSUP 7 V ≤ VSUP ≤ 18 V, tBIT = 96 µs tDOM(MAX)_D4 - tREC(MIN)_D4 |
17.28 | µs | ||
Tr-d max_low | Low battery transmitter propagation delay timings for the duty cycle(1)
(2)
(6) Recessive to dominant |
THREC(MAX) = 0.665 x VSUP, THDOM(MAX) = 0.499 x VSUP 5.5 V ≤ VSUP ≤ 7 V, tBIT = 52 µs tREC(MAX)_low - tDOM(MIN)_low |
10.8 | µs | ||
Td-r max_low | Low battery transmitter propagation delay timings for the duty cycle(1)
(2)
(6) Dominant to recessive |
THREC(MAX) = 0.496 x VSUP
THDOM(MAX) = 0.361 x VSUP 6.1 V ≤ VSUP ≤ 7 V, tBIT = 52 µs tDOM(MAX)_low - tREC(MIN)_low |
8.4 | µs |