SLLSFE4A May 2022 – December 2022 TLIN1431-Q1
PRODUCTION DATA
The nRST output pin behavior depends upon the reason the device entered restart mode. When entered from other modes due to a watchdog failure, soft reset or an external nRST toggle, the nRST pin is pulled low for tnRST_TOG which is a default pulse width of 2 ms. This pulse width can be configured to 15 ms by changing register 8'h29[5] = 1b. In pin control, the pulse width on nRST is always nominally 15 ms for a watchdog failure. Once the timer expires, the device enters standby mode. From power up, sleep and certain fail-safe modes, the nRST behaves like the UVCC event, pulling nRST low until VCC > UVCC and tRSTN_act times out. See Figure 8-41 on how the nRST pin behaves when entering restart mode.
The nRST pin is also a TLIN1431x-Q1 reset input which transitions the device into restart mode when the pin is pulled low for tnRSTIN.