SLLSFE4A May   2022  – December 2022 TLIN1431-Q1

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 ESD Ratings, IEC Specification
    4. 6.4 Recommended Operating Conditions
    5. 6.5 Thermal Information
    6. 6.6 Power Supply Characteristics
    7. 6.7 Electrical Characteristics
    8. 6.8 AC Switching Characteristics
    9. 6.9 Typical Characteristics
  7. 7 Parameter Measurement Information
    1. 7.1 Test Circuit: Diagrams and Waveforms
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  LIN (Local Interconnect Network) Bus
        1. 8.3.1.1 LIN Transmitter Characteristics
        2. 8.3.1.2 LIN Receiver Characteristics
          1. 8.3.1.2.1 Termination
      2. 8.3.2  TXD (Transmit Input and Output)
      3. 8.3.3  RXD (Receive Output)
      4. 8.3.4  WAKE (High Voltage Local Wake Up Input)
      5. 8.3.5  WDT or CLK (Pin Programmable Watchdog Delay Input or SPI Clock)
      6. 8.3.6  WDI or SDI (Watchdog Timer Input or SPI Serial Data In)
      7. 8.3.7  PIN or nCS (Pin Watchdog Select or SPI Chip Select)
      8. 8.3.8  LIMP (Limp Home Output – High Voltage Open Drain Output)
        1. 8.3.8.1 LIMP in Pin Control Mode
        2. 8.3.8.2 LIMP in SPI Control Mode
      9. 8.3.9  nWDR/SDO (Watchdog Timeout Reset Output/SPI Serial Data Out)
      10. 8.3.10 HSS (High-side Switch)
      11. 8.3.11 HSSC or FSO (High-side Switch Control or Function Output)
      12. 8.3.12 WKRQ or INH (Wake Request or Inhibit)
      13. 8.3.13 PV
      14. 8.3.14 DIV_ON
      15. 8.3.15 VBAT (Battery Voltage)
      16. 8.3.16 VSUP (Supply Voltage)
      17. 8.3.17 GND (Ground)
      18. 8.3.18 EN or nINT (Enable Input or Interrupt Output)
      19. 8.3.19 nRST (Reset Input and Reset Output)
      20. 8.3.20 VCC (Supply Output)
      21. 8.3.21 VBAT Voltage Divider
      22. 8.3.22 Protection Features
        1. 8.3.22.1  Sleep Wake Error (SWE) Timer
        2. 8.3.22.2  Device Reset
        3. 8.3.22.3  TXD Dominant Time Out (DTO)
        4. 8.3.22.4  Bus Stuck Dominant System Fault: False Wake Up Lockout
        5. 8.3.22.5  Thermal Shutdown
        6. 8.3.22.6  Under-voltage on VSUP
        7. 8.3.22.7  Unpowered Device and LIN Bus
        8. 8.3.22.8  Floating Pins
        9. 8.3.22.9  VCC Voltage Regulator
          1. 8.3.22.9.1 Under or Over Voltage and Short Circuit
          2. 8.3.22.9.2 Output Capacitance Selection
          3. 8.3.22.9.3 Low-Voltage Tracking
          4. 8.3.22.9.4 Power Supply Recommendation
        10. 8.3.22.10 Watchdog
          1. 8.3.22.10.1 Watchdog in Pin Control Mode
          2. 8.3.22.10.2 Watchdog in SPI Control Mode
          3. 8.3.22.10.3 Watchdog Error Counter
          4. 8.3.22.10.4 Pin Control Mode
          5. 8.3.22.10.5 SPI Control Programming
          6. 8.3.22.10.6 Watchdog Register Relationship
          7. 8.3.22.10.7 Watchdog Timing
      23. 8.3.23 Channel Expansion
        1. 8.3.23.1 Channel Expansion for LIN
        2. 8.3.23.2 Channel Expansion for CAN Transceiver
    4. 8.4 Device Functional Modes
      1. 8.4.1 Init Mode
      2. 8.4.2 Normal Mode
      3. 8.4.3 Fast Mode
      4. 8.4.4 Sleep Mode
      5. 8.4.5 Standby Mode
      6. 8.4.6 Restart Mode
        1. 8.4.6.1 Restart Counter
        2. 8.4.6.2 nRST Behavior in Restart Mode
      7. 8.4.7 Fail-safe Mode
      8. 8.4.8 Wake Up Events
        1. 8.4.8.1 Wake Up Request (RXD)
        2. 8.4.8.2 Local Wake Up (LWU) via WAKE Terminal
          1. 8.4.8.2.1 Static WAKE
          2. 8.4.8.2.2 Cyclic Sense Wake
      9. 8.4.9 Mode Transitions
    5. 8.5 Programming
      1. 8.5.1 SPI Communication
        1. 8.5.1.1 Cyclic Redundancy Check
        2. 8.5.1.2 Chip Select Not (nCS)
        3. 8.5.1.3 Serial Clock Input (CLK)
        4. 8.5.1.4 Serial Data Input (SDI)
        5. 8.5.1.5 Serial Data Output (SDO)
    6. 8.6 Registers
      1. 8.6.1  DEVICE_ID_y Register (Address = 0h + formula) [reset = 0h]
      2. 8.6.2  REV_ID_MAJOR Register (Address = 8h) [reset = 01h]
      3. 8.6.3  REV_ID_MINOR Register (Address = 9h) [reset = 0h]
      4. 8.6.4  CRC_CNTL Register (Address = Ah) [reset = 0h]
      5. 8.6.5  CRC_POLY_SET (Address = Bh) [reset = 00h]
      6. 8.6.6  Scratch_Pad_SPI Register (Address = Fh) [reset = 0h]
      7. 8.6.7  WAKE_PIN_CONFIG1 Register (Address = 11h) [reset = 04h]
      8. 8.6.8  WAKE_PIN_CONFIG2 Register (Address = 12h) [reset = 2h]
      9. 8.6.9  WD_CONFIG_1 Register (Address = 13h) [reset = 90h]
      10. 8.6.10 WD_CONFIG_2 Register (Address = 14h) [reset = 02h]
      11. 8.6.11 WD_INPUT_TRIG Register (Address = 15h) [reset = 0h]
      12. 8.6.12 WD_RST_PULSE Register (Address = 16h) [reset = 40h]
      13. 8.6.13 FSM_CONFIG Register (Address = 17h) [reset = 0h]
      14. 8.6.14 FSM_CNTR Register (Address = 18h) [reset = 0h]
      15. 8.6.15 DEVICE_RST Register (Address = 19h) [reset = 0h]
      16. 8.6.16 DEVICE_CONFIG (Address = 1Ah) [reset = 80h]
      17. 8.6.17 DEVICE_CONFIG2 (Address = 1Bh) [reset = 0h]
      18. 8.6.18 SWE_TIMER (Address = 1Ch) [reset = 30h]
      19. 8.6.19 LIN_CNTL (Address = 1Dh) [reset = 00h]
      20. 8.6.20 HSS_CNTL (Address = 1Eh) [reset = 0h]
      21. 8.6.21 PWM1_CNTL1 (Address = 1Fh) [reset = 0h]
      22. 8.6.22 PWM1_CNTL2 (Address = 20h) [reset = 0h]
      23. 8.6.23 PWM1_CNTL3 (Address = 21h) [reset = 00h]
      24. 8.6.24 PWM2_CNTL1 (Address = 22h) [reset = 0h]
      25. 8.6.25 PWM2_CNTL2 (Address = 23h) [reset = 0h]
      26. 8.6.26 PWM2_CNTL3 (Address = 24h) [reset = 0h]
      27. 8.6.27 TIMER1_CONFIG (Address = 25h) [reset = 00h]
      28. 8.6.28 TIMER2_CONFIG (Address = 26h) [reset = 00h]
      29. 8.6.29 RSRT_CNTR (Address = 28h) [reset = 40h]
      30. 8.6.30 nRST_CNTL (Address = 29h) [reset = 00h]
      31. 8.6.31 INT_GLOBAL Register (Address = 50h) [reset = A0h]
      32. 8.6.32 INT_1 Register (Address = 51h) [reset = 0h]
      33. 8.6.33 INT_2 Register (Address = 52h) [reset = 40h]
      34. 8.6.34 INT_3 Register (Address 53h) [reset = 0h]
      35. 8.6.35 INT_EN_1 Register (Address = 56h) [reset = B0h]
      36. 8.6.36 INT_EN_2 Register (Address = 57h) [reset = 37h]
      37. 8.6.37 INT_EN_3 Register (Address =58h) [reset = BCh]
      38. 8.6.38 INT_4 Register (Address = 5Ah) [reset = 0h]
      39. 8.6.39 INT_EN_4 Register (Address = 5Eh) [reset = CCh]
      40. 8.6.40 Reserved Registers
  9. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Device Brownout Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
        1. 9.2.1.1 Normal Mode Application Note
        2. 9.2.1.2 Standby Mode Application Note
        3. 9.2.1.3 TXD Dominant State Timeout Application Note
      2. 9.2.2 Detailed Design Procedures
      3. 9.2.3 Application Curves
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  10. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Related Documentation
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 Support Resources
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 Glossary
  11. 11Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8.6.37 INT_EN_3 Register (Address =58h) [reset = BCh]

INT_EN_3 is shown in Figure 8-91 and described in Table 8-47.

Return to Summary Table.

Interrupt mask for INT_3.

Figure 8-91 INT_EN_3 Register
76543210
SPIERR_ENRSVDFSM_ENCRCERR_ENVCCSC_ENRSRT_CNT_ENRSVD
R/W-1bR-0bR/W-1bR/W-1bR/W-1bR/W-1bR-0b
Table 8-47 INT_EN_3 Register Field Descriptions
BitFieldTypeResetDescription
7SPIERR_ENR/W1bSPI error interrupt enable
6RSVDR0bReserved
5FSM_ENR/W1bFail-safe mode interrupt enable
4CRCERR_ENR/W1bSPI CRC error interrupt enable
3VCCSC_ENR/W1bVCC short circuit interrupt enable
2RSRT_CNT_ENR/W1bExceeding programmed restart counter interrupt enable
1-0RSVDR0bReserved