SLLSFE4A May 2022 – December 2022 TLIN1431-Q1
PRODUCTION DATA
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
RXD Output Terminal | ||||||
VOH | High level output voltage | IO = –2 mA, VCC = Active | 0.8 | VCC | ||
VOL | Low level output voltage | IO = 2 mA, VCC = Active | 0.2 | VCC | ||
ILKG(OFF) | Unpowered leakage current | Outputs = 5.25/3.465 V, VCC = VSUP = 0 V | –1 | 1 | µA | |
TXD Input Terminal | ||||||
VIL | Low level input voltage | –0.3 | 0.8 | V | ||
VIH | High level input voltage | 2 | 5.5 | V | ||
IIH | High level input leakage current | TXD = VIH | –5 | 0 | 5 | µA |
RTXD | Internal pull-up resistor value | 125 | 350 | 800 | kΩ | |
LIN Terminal (Referenced to VSUP) | ||||||
VOH | HIGH level output voltage(5) | LIN recessive, TXD = high, IO = 0 mA, VSUP = 5.5 V to 28 V | 0.85 | VSUP | ||
VOL | LOW level output voltage(5) | LIN dominant, TXD = low, VSUP = 5.5 V to 28 V | 0.2 | VSUP | ||
VSUP_NON_OP | VSUP where impact of recessive LIN bus < 5% (ISO/DIS 17987 Param 11) | TXD & RXD open VLIN = 5.5 V to 45 V | –0.3 | 45 | V | |
I BUS_LIM | Limiting current (ISO/DIS 17987 Param 12) | TXD = 0 V, VLIN = 28 V, RMEAS = 440 Ω, VSUP = 28 V, VBUSdom ≤ 0.251 * VSUP |
40 | 90 | 200 | mA |
I BUS_PAS_dom | Receiver leakage current, dominant (ISO/DIS 17987 Param 13) | VLIN = 0 V, VSUP = 12 V Driver off/recessive | –1 | mA | ||
I BUS_PAS_rec1 | Receiver leakage current, recessive (ISO/DIS 17987 Param 14) | VLIN ≥ VSUP, 5.5 V ≤ VSUP ≤ 28 V Driver off | 20 | µA | ||
I BUS_PAS_rec2 | Receiver leakage current, recessive (ISO/DIS 17987 Param 14) | VLIN = VSUP, Driver off | –5 | 5 | µA | |
I BUS_NO_GND | Leakage current, loss of ground (ISO/DIS 17987 Param 15) | GND = VSUP, VSUP = 12 V, 0 V ≤ VLIN ≤ 28 V | –1 | 1 | mA | |
IBUS_NO_BAT | Leakage current, loss of supply (ISO/DIS 17987 Param 16) | 0 V ≤ VLIN ≤ 28 V, VSUP = GND | 10 | µA | ||
VBUSdom | Low level input voltage (ISO/DIS 17987 Param 17) | LIN dominant (including LIN dominant for wake up); Figure 7-2 | 0.4 | VSUP | ||
VBUSrec | High level input voltage (ISO/DIS 17987 Param 18) | LIN recessive; Figure 7-2 | 0.6 | VSUP | ||
VBUS_CNT | Receiver center threshold (ISO/DIS 17987 Param 19) | VBUS_CNT = (VIL + VIH)/2; Figure 7-2 | 0.475 | 0.5 | 0.525 | VSUP |
VHYS | Hysteresis voltage (ISO/DIS 17987 Param 20)(6)(7) | VHYS = (VIL - VIH); Figure 7-2 | 0.175 | VSUP | ||
VSERIAL_DIODE | Serial diode LIN term pull-up path (ISO/DIS 17987 Param 21) | By design and characterization | 0.4 | 0.7 | 1.0 | V |
RLIN | Internal pull-up resistor to VSUP on LIN (ISO/DIS 17987 Param 26) | Normal and Standby modes | 20 | 45 | 60 | kΩ |
IRSLEEP | Pull-up current source to VSUP | Sleep mode, VSUP = 12 V, LIN = GND | –20 | –2 | µA | |
CLIN,PIN | Capacitance of the LIN pin | By design and characterization | 25 | pF | ||
EN Input Terminal | ||||||
VIH | High level input voltage | 2 | 5.5 | V | ||
VIL | Low level input voltage | 0.8 | V | |||
VHYS | Hysteresis voltage | By design and characterization | 30 | 500 | mV | |
IIL | Low level input current | EN = Low | –8 | 8 | µA | |
REN | Internal pull-down resistor | 125 | 350 | 800 | kΩ | |
LIMP Output Terminal (High Voltage Open-drain Output) | ||||||
ΔVH | Hi-level voltage drop for LIMP with respect to VSUP | ILIMP = –60 mA | 0.42 | 1.2 | V | |
Rdson | LIMP output drain-to-source on resistance | IO = –60 mA | 7 | 20 | Ω | |
ILKG(LIMP) | Leakage current | LIMP = 0 V, Sleep Mode | –1 | 1 | µA | |
HSS, INH high voltage open drain output pin | ||||||
VDET_INH | Voltage on INH/WKRQ pin during tDET_INH time | VSUP = 14V | 1.5 | V | ||
ΔVHINH | Hi-level voltage drop for INH with respect to VSUP | IINH = –6 mA | 0.5 | 1 | V | |
ΔVHHSS | Hi-level voltage drop for HSS with respect to VSUP | IHSS = –60 mA | 0.42 | 1.2 | V | |
Rdson | HSS output drain-to-source on resistance | IO = –60 mA | 7 | 17 | Ω | |
IO(HSS) | Output current support | VSUP = 14 V, | 60 | 100 | mA | |
IOC(HSS) | HSS overcurrent limit | VSUP = 14 V | 150 | 300 | mA | |
IOL(HSS) | HSS open load current | VSUP = 14 V | –2.5 | mA | ||
IOLHYS(HSS) | HSS open load current hysteresis | VSUP = 14 V | 0.05 | 0.45 | 1 | mA |
Ilkg | Leakage current | INH, HSS = 0 V, Sleep Mode | –1 | 1 | µA | |
tR/F | Output rise and fall times (HSS) | 5.5 V ≤ VSUP ≤ 28 V, ILOAD = 60 mA, RL = 220 Ω, 80%/20% | 0.6 | 2.5 | V/µs | |
tHSS_on | Switching on delay (HSS) from SPI command to on | VSUP = 14 V, ILOAD = 60 mA, VOUT = 80% of VSUP | 60 | µs | ||
tHSS_off | Switching off delay (HSS) from SPI command to off | VSUP = 14 V, ILOAD = 60 mA, VOUT = 20% of VSUP | 140 | µs | ||
tOCFLTR | HSS overcurrent filter time(2) | VSUP = 14 V | 16 | µs | ||
tOLFLTR | HSS open load filter time(2) | VSUP = 14 V | 64 | µs | ||
tOCOFF | HSS overcurrent shut off time | IO(HSS) > IOC(HSS) | 200 | 300 | µs | |
WAKE Input Terminal | ||||||
VIH | High-level input voltage | Sleep or Standby Mode, WAKE pin enabled | 4 | V | ||
VIL | Low-level input voltage | Sleep or Standby Mode, WAKE pin enabled | 2 | V | ||
IIL | Low-level input leakage current | WAKE = 1 V | 15 | 25 | µA | |
tWAKE | Wake up hold time from a wake edge on WAKE in standby or sleep mode for static sensing.. | See Figure 8-44 and Figure 8-45 | 140 | µs | ||
tWAKE_INVALID | WAKE pin pulses shorter than this will be filtered out in standby or sleep mode for static and cyclic sensing. | See Figure 8-44 and Figure 8-45 | 10 | µs | ||
WDI, SDI, CLK, nCS Input Terminal | ||||||
VIH | High-level input voltage | 2.19 | V | |||
VIL | Low-level input voltage | 0.8 | V | |||
IIH | High-level input leakage current | Inputs = VCC | –1 | 1 | µA | |
IIL | Low-level input leakage current | Inputs = 0 V, VCC = Active | –50 | µA | ||
CIN | Input Capacitance | 4 MHz | 10 | 15 | pF | |
ILKG(OFF) | Unpowered leakage current | Inputs = 5.25/3.465 V, VCC = VSUP = 0 V | –1 | 1 | µA | |
RWDI_SDIpu | Internal pull-up resistor on WDI/SDI pin | 100 | 240 | 400 | kΩ | |
RCLKpu | Internal pull-up resistor on WDT/CLK pin | SPI control only for CLK | 100 | 240 | 400 | kΩ |
RnCSpu | Internal pull-up resistor on PIN/nCS pin | SPI control only for nCS | 100 | 240 | 400 | kΩ |
WDT Input Terminal | ||||||
VIH | High-level input voltage | Inputs = VCC | 0.8 | VCC | ||
VIL | Low-level input voltage | Inputs = VCC | 0.2 | VCC | ||
VIM(WDT) | WDT Mid-level input voltage(1) | Inputs = VCC | 0.4 | 0.5 | 0.6 | VCC |
IIH | High-level input leakage current | Inputs = VCC | 2.5 | 25 | µA | |
IIL | Low-level input leakage current | Inputs = 0 V, VCC = Active | –25 | –2.5 | µA | |
ILKG(OFF) | Unpowered leakage current | Inputs = 5.25/3.465 V, VCC = VSUP = 0 V | –3 | 3 | µA | |
SDO Output Terminal | ||||||
VOH | High level output voltage | IO = –2 mA, VCC = Active | 0.8 | VCC | ||
VOL | Low level output voltage | IO = 2 mA, VCC = Active | 0.2 | VCC | ||
ILKG(OFF) | Unpowered leakage current | Outputs = 5.25/3.465 V, VCC = VSUP = 0 V | –1 | 1 | µA | |
nRST Terminal; input/output reset (Open-drain) | ||||||
ILKG | Leakage current, high-level | LIN = VSUP, nRST = VCC | –5 | 5 | µA | |
VOL | Low-level output voltage | Based upon external pull up to VCC | 0.2 | VCC | ||
IOL | Low-level output current, open drain | LIN = 0 V, nRST = 0.4 V | 1.5 | mA | ||
Vth(sw) | Switching threshold voltage | 0.25 | 0.75 | VCC | ||
RPU | Pull-up resistance | 30 | 45 | 65 | kΩ | |
nINT, nWDR, WKRQ Terminal | ||||||
VOH | High level output voltage | IO = –2 mA, VCC = Active | 0.8 | VCC | ||
VOL | Low-level output voltage | IO = 2 mA, VCC = Active | 0.2 | VCC | ||
ILKG(OFF) | Unpowered leakage current (nINT and nWDR pins) | Outputs = 5.25/3.465 V, VCC = VSUP = 0 V | –1 | 1 | µA | |
HSSC | ||||||
VIH | High-level input voltage | 2 | 5.5 | V | ||
VIL | Low-level input voltage | 0.8 | V | |||
IIL | Low-level input current | VIN = 0 V | –1 | 1 | µA | |
RHSSC | Pull-down resistor | 150 | 350 | 800 | kΩ | |
fSW | Switching frequency | VHSS = 14 V, IO(HSS) = 60 mA | 400 | Hz | ||
WDI, WDT TIMING and SWITCHING CHARACTERISTIC (RL = 1 MΩ, CL = 50 pF and TJ = -40°C to 150°C) | ||||||
tW | WDI pulse width; see Figure 7-8 | Filter time to avoid false input | 30 | µs | ||
tWINDOW | Closed Window + Open Window; See Figure 7-8 | WDT = GND | 32 | 40 | 48 | ms |
WDT = VCC | 480 | 600 | 720 | ms | ||
WDT = Floating | 4.8 | 6 | 7.2 | s | ||
DIV_ON | ||||||
VIH | High-level input voltage | 2 | 5.5 | V | ||
VIL | Low-level input voltage | 0.8 | V | |||
IIL | Low-level input current | VDIV_ON = 0 V | –1 | 1 | µA | |
RDIV_ON | Pull-down resistor | 150 | 370 | 800 | kΩ | |
PV | ||||||
Ratio | Divider ratio 5 V VCC | VBAT = 5.5 V to 28 V | 1:7 | |||
Ratio | Divider ratio 3.3 V VCC | VBAT = 5.5 V to 20 V | 1:9 | |||
ERR | Divider ratio error | VBAT = 5.5 V to 28 V | –2 | 2 | % | |
VBATLIN5 | Linear voltage range for VBAT for 5 V LDO (3) | RLOAD = 470 Ω ± 5% and CLOAD = 10 nF ± 10%; When capacitive load only 20 pF ± 20%, 5.5 V ≤ VBAT ≤ 28 V | 0.735 | 4.05 | V | |
VBATLIN3 | Linear voltage range for VBAT for 3.3 V LDO and when I/O is 3.3 V with 5 V LDO (4) | RLOAD = 470 Ω ± 5% and CLOAD = 10 nF ± 10%; When capacitive load only 20 pF ± 20%, 5.5 V ≤ VBAT ≤ 20 V | 0.561 | 2.27 | V | |
VMAX5V | Maximum VPVOUT | 28 V < VBAT ≤ 42 V, 470 Ω ± 5% and CLOAD = 10 nF ± 10%; When capacitive load only 20 pF ± 20% | 5.1 | V | ||
VMAX3.3V | Maximum VPVOUT for 3.3 V LDO and when I/O is 3.3 V with 5 V LDO | 20 V < VBAT ≤ 42 V, 470 Ω ± 5% and CLOAD = 10 nF ± 10%; When capacitive load only 20 pF ± 20% | 3.36 | V | ||
VVCC5V_VIO3V | Voltage when VCC = 5 V and I/O is at 3.3 V | RLOAD = 470 Ω ± 5% and CLOAD = 10 nF ± 10%; When capacitive load only 20 pF ± 20% and I/O voltage is ≤ 3.6 V | 3.36 | V | ||
CPIN | Pin capacitance | 12 | pF | |||
tSET | Settling time of the buffer | 470 Ω ± 5% and CLOAD = 10 nF ± 10%; When capacitive load only 20 pF ± 20% | 50 | µs | ||
Duty Cycle Characteristics | ||||||
D1 | Duty Cycle 1 (ISO/DIS 17987 Param 27 and J2602 Normal battery)(8)(9) | THREC(MAX) = 0.744 x VSUP, THDOM(MAX) = 0.581 x VSUP, VSUP = 7 V to 18 V, tBIT = 50/52 µs, D1 = tBUS_rec(min)/(2 x tBIT) (See Figure 7-3, Figure 7-4) |
0.396 | |||
D2 | Duty Cycle 2 (ISO/DIS 17987 Param 28 and J2602 Normal battery)(8)(9) | THREC(MIN) = 0.422 x VSUP, THDOM(MIN) = 0.284 x VSUP, VSUP = 7.6 V to 18 V, tBIT = 50/52 µs, D2 = tBUS_rec(MAX)/(2 x tBIT) (See Figure 7-3, Figure 7-4) |
0.581 | |||
D3 | Duty Cycle 3 (ISO/DIS 17987 Param 29 and J2602 Normal battery)(8)(9) | THREC(MAX) = 0.778 x VSUP, THDOM(MAX) = 0.616 x VSUP, VSUP = 7.0 V to 18 V, tBIT = 96 µs, D3 = tBUS_rec(min)/(2 x tBIT) (See Figure 7-3, Figure 7-4) | 0.417 | |||
D4 | Duty Cycle 4 (ISO/DIS 17987 Param 30 and J2602 Normal battery)(8)(9) | THREC(MIN) = 0.389 x VSUP, THDOM(MIN) = 0.251 x VSUP, VSUP = 7.6 V to 18 V, tBIT = 96 µs, D4 = tBUS_rec(MAX)/(2 x tBIT) (See Figure 7-3, Figure 7-4) |
0.59 | |||
D1LB | Duty Cycle 1 J2602 Low battery(9)(10) |
THREC(MAX) = 0.665 x VSUP, THDOM(MAX) = 0.499 x VSUP, VSUP = 5.5 V to 7 V, tBIT = 50/52 µs, D1 = tBUS_rec(min)/(2 x tBIT) (See Figure 7-3, Figure 7-4) | 0.396 | |||
D2LB | Duty Cycle 2 J2602 Lowl battery(9)(10) |
THREC(MIN) = 0.496 x VSUP, THDOM(MIN) = 0.361 x VSUP, VSUP = 6.1 V to 7.6 V, tBIT = 50/52 µs, D2 = tBUS_rec(MAX)/(2 x tBIT) (See Figure 7-3, Figure 7-4) | 0.581 | |||
D3LB | Duty Cycle 3 J2602 Low battery(9)(10) |
THREC(MAX) = 0.665 x VSUP, THDOM(MAX) = 0.499 x VSUP, VSUP = 5.5 V to 7 V, tBIT = 96 µs, D1 = tBUS_rec(min)/(2 x tBIT) (See Figure 7-3, Figure 7-4) | 0.417 | |||
D4LB | Duty Cycle 4 J2602 Lowl battery(9)(10) |
THREC(MIN) = 0.496 x VSUP, THDOM(MIN) = 0.361 x VSUP, VSUP = 6.1 V to 7.6 V, tBIT = 96 µs, D2 = tBUS_rec(MAX)/(2 x tBIT) (See Figure 7-3, Figure 7-4) | 0.59 |