SLLSFE4A May 2022 – December 2022 TLIN1431-Q1
PRODUCTION DATA
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
Device Switching Characteristics | ||||||
trx_pdr trx_pdf |
Receiver rising/falling propagation delay time (ISO/DIS 17987 Param 31) | RRXD = 2.4 kΩ, CRXD = 20 pF (See Figure 7-3, Figure 7-4) | 6 | µs | ||
trs_sym | Symmetry of receiver propagation delay time Receiver rising propagation delay time (ISO/DIS 17987 Param 32) | Rising edge with respect to falling edge, (trx_sym = trx_pdf – trx_pdr), RRXD = 2.4 kΩ, CRXD = 20 pF (See Figure 7-3, Figure 7-4) | –2 | 2 | µs | |
tLINBUS | LIN wakeup time (minimum dominant time on LIN bus for wakeup) | See Figure 7-6, Figure 8-11 and Figure 8-12 | 25 | 100 | 150 | µs |
tCLEAR | Time to clear false wakeup prevention logic if LIN bus had a bus stuck dominant fault (recessive time on LIN bus to clear bus stuck dominant fault) | See Figure 8-12 | 10 | 60 | µs | |
tTXD_DTO | Dominant state time out | 20 | 45 | 80 | ms | |
tEN | Enable pin deglitch time | Time enable pin state change before initiating mode change or sampling TXD pin | 3 | 12 | µs | |
tMODE_CHANGE | Mode change delay time | Time to change from normal mode to sleep mode through EN pin: See Figure 7-5 | 100 | µs | ||
tDETECT | Time to detect Pin vs SPI and I/O voltage level at power up(1) | Time from coming out of UVCC and device determines these states | 2 | µs | ||
tDET_INH | Time to detect which output INH or WKRQ at power up | Time from coming out of UVCC and device determines these states | 25 | µs | ||
tNOMINIT | Normal mode initialization time | Time for normal mode to initialize and data on RXD pin to be valid, includes tMODE_CHANGE for standby mode to normal mode See Figure 7-5 | 45 | µs | ||
tRSTN_act | Time required for VCC ≥ UVCC to leave Restart mode | VCC ≥ UVCC | 1.5 | 2 | 2.5 | ms |
tnRSTIN | Input pulse required on the nRST pin to recognize a device reset. | 120 | µs | |||
tNRST_TOG | nRST pin output toggle high to low to high time | reg 29h[5] = 0 (Default value in SPI control. Value in pin control except for watchdog failure.) | 1.5 | 2 | 2.5 | ms |
reg 29h[5] = 1 (Value in pin control for watchdog failure.) | 10 | 15 | 20 | ms | ||
tINITWD | Initial long watchdog window time required to trigger first watchdog input trigger when entering Standby mode or Normal mode | WDI input trigger or SPI write command | 150 | 200 | ms | |
tINACT_FS | Timer for inactivity coming out of sleep mode and when coming out of failsafe mode to determine if caused event has been cleared (1) | Default values and can be programmed to different values in SPI control. | 4 | 5 | 6 | min |
tPWRUP | Time from VSUP exceeding UVSUP until INH active | VCC > UVCC, INH = VSUP, VCC load of 50 mA @ 22 µF capacitance | 3 | ms | ||
Time from VSUP exceeding UVSUP and VCC exceeding UVCC until WKRQ active | VCC > UVCC, WKRQ = VCC, VCC load of 50 mA @ 22 µF capacitance | 3 | ms | |||
tTOGGLE | RXD pulse width when waking from sleep mode | register 'h12[2] = 1 | 5 | 15 | µs | |
tUVFLTR | Undervoltage detection delay time for VCC | 3 | 4 | ms | ||
tVSC | Short to ground on VCC detection delay time | 75 | 100 | 130 | µs | |
tLDOON | Time LDO is on to determine if a short circuit event is present after a previous uncleared detection | 2 | 3 | ms | ||
tMODE_STBY_NOM | Standby to normal mode change time based upon SPI write | 70 | µs | |||
tMODE_NOM_SLP | SPI write to go to sleep from normal | Time from SPI sleep command where LIN transceiver is off and RXD doesn't reflect the LIN bus | 200 | µs | ||
tMODE_NOM_STBY | SPI write to go to standby from normal mode | 70 | µs | |||
tWKRQ_SLP | Time WKRQ turns on after a wake event when device is in sleep mode | Dependent upon LDO turning on and ramp time. Time provided is based upon 1 µs ramp and LDO being at 2 V. | 450 | µs | ||
tINH_SLP | Time INH turns on after a wake event when device is in sleep mode | 210 | µs | |||
tINH_NOM_SLP | SPI write to go to sleep from normal mode and INH turns off | 70 | µs | |||
tWK_WIDTH_MIN | Minimum WAKE pin pulse width (SPI mode only) (2) (3) (4) | Minimum WAKE Pin pulse width Register 8'h11[3:2] = 00b; See Figure 8-46 | 10 | ms | ||
Minimum WAKE Pin pulse width Register 8'h11[3:2] = 01b; See Figure 8-46 | 20 | ms | ||||
Minimum WAKE Pin pulse width Register 8'h11[3:2] = 10b; See Figure 8-46 | 40 | ms | ||||
Minimum WAKE Pin pulse width Register 8'h11[3:2] = 11b; See Figure 8-46 | 80 | ms | ||||
tWK_WIDTH_INVALID | Maximum Pulse width that is considered invalid (SPI mode only) (2) (3) | Maximum WAKE Pin pulse width that is considered invalid Register 8'h11[3:2] = 00b; See Figure 8-46 | 5 | ms | ||
Maximum WAKE Pin pulse width that is considered invalid Register 8'h113:2] = 01b; See Figure 8-46 | 10 | ms | ||||
Maximum WAKE Pin pulse width that is considered invalid Register 8'h11[3:2] = 10b; See Figure 8-46 | 20 | ms | ||||
Maximum WAKE Pin pulse width that is considered invalid Register 8'h11[3:2] = 11b; See Figure 8-46 | 40 | ms | ||||
tWK_WIDTH_MAX | Maximum WAKE pin pulse width to be considered valid (SPI mode only) (2) | Maximum WAKE Pin pulse window Register 8'h11[1:0] = 00b; See Figure 8-46 | 750 | 950 | ms | |
Maximum WAKE Pin pulse window Register 8'h11[1:0] = 01b; See Figure 8-46 | 1000 | 1250 | ms | |||
Maximum WAKE Pin pulse window Register 8'h11[1:0] = 10b; See Figure 8-46 | 1500 | 1875 | ms | |||
Maximum WAKE Pin pulse window Register 8'h11[1:0] = 11b; See Figure 8-46 | 2000 | 2500 | ms | |||
tWK_CYC | Sampling window for cyclic sensing wake; Standby or Sleep mode; see Figure 8-49 | Register 8'h12[5] = 0 | 10 | 30 | 40 | µs |
Register 8'h12[5] = 1 | 60 | 75 | 90 | µs | ||
Fast Mode | ||||||
DR | Data Rate | 5.5 V ≤ VSUP ≤ 18 V, RLIN = 500 Ω and CLIN(bus) = 600 pF | 200 | kbps | ||
trx_pdr trx_pdf |
Receiver rising/falling propagation delay time (ISO/DIS 17987 Param 31) | RRXD = 2.4 kΩ, CRXD = 20 pF (See Figure 7-3, Figure 7-4 | 5 | µs | ||
ttxr/f | LIN transmitter rise and fall time | 5.5 V ≤ VSUP ≤ 18 V, RLIN = 500 Ω and CLIN(bus) = 600 pF, 80%/20% | 1.5 | µs | ||
tFM_CHANGE | Fast mode determination time for entering or leaving | Based upon EN and TXD voltage levels | 70 | 90 | 110 | µs |
tFMTXD | TXD pin pulse width to enter fast mode | Pulse must start after tEN and finish before tFM_CHANGE | 5 | 25 | µs | |
SPI Switching Characteristics | ||||||
fSCK | SCK, SPI clock frequency (1) | 4 | MHz | |||
tSCK | SCK, SPI clock period (1) | See Figure 7-7 | 250 | ns | ||
tRSCK | SCK rise time (1) | See Figure 7-7 | 40 | ns | ||
tFSCK | SCK fall time (1) | See Figure 7-7 | 40 | ns | ||
tSCKH | SCK, SPI clock high (1) | See Figure 7-7 | 125 | ns | ||
tSCKL | SCK, SPI clock low (1) | See Figure 7-7 | 125 | ns | ||
tACC | First read access time from chip select (1) | See Figure 7-7 | 50 | ns | ||
tCSS | Chip select setup time (1) | See Figure 7-7 | 100 | ns | ||
tCSH | Chip select hold time (1) | See Figure 7-7 | 100 | ns | ||
tCSD | Chip select disable time (1) | See Figure 7-7 | 50 | ns | ||
tSISU | Data in setup time (1) | See Figure 7-7 | 50 | ns | ||
tSIH | Data in hold time (1) | See Figure 7-7 | 50 | ns | ||
tSOV | Data out valid (1) | See Figure 7-7 | 80 | ns | ||
tRSO | SO rise time (1) | See Figure 7-7 | 40 | ns | ||
tFSO | SO fall time (1) | See Figure 7-7 | 40 | ns |