SLLSFE4A May   2022  – December 2022 TLIN1431-Q1

PRODUCTION DATA  

  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 ESD Ratings, IEC Specification
    4. 6.4 Recommended Operating Conditions
    5. 6.5 Thermal Information
    6. 6.6 Power Supply Characteristics
    7. 6.7 Electrical Characteristics
    8. 6.8 AC Switching Characteristics
    9. 6.9 Typical Characteristics
  7. Parameter Measurement Information
    1. 7.1 Test Circuit: Diagrams and Waveforms
  8. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  LIN (Local Interconnect Network) Bus
        1. 8.3.1.1 LIN Transmitter Characteristics
        2. 8.3.1.2 LIN Receiver Characteristics
          1. 8.3.1.2.1 Termination
      2. 8.3.2  TXD (Transmit Input and Output)
      3. 8.3.3  RXD (Receive Output)
      4. 8.3.4  WAKE (High Voltage Local Wake Up Input)
      5. 8.3.5  WDT or CLK (Pin Programmable Watchdog Delay Input or SPI Clock)
      6. 8.3.6  WDI or SDI (Watchdog Timer Input or SPI Serial Data In)
      7. 8.3.7  PIN or nCS (Pin Watchdog Select or SPI Chip Select)
      8. 8.3.8  LIMP (Limp Home Output – High Voltage Open Drain Output)
        1. 8.3.8.1 LIMP in Pin Control Mode
        2. 8.3.8.2 LIMP in SPI Control Mode
      9. 8.3.9  nWDR/SDO (Watchdog Timeout Reset Output/SPI Serial Data Out)
      10. 8.3.10 HSS (High-side Switch)
      11. 8.3.11 HSSC or FSO (High-side Switch Control or Function Output)
      12. 8.3.12 WKRQ or INH (Wake Request or Inhibit)
      13. 8.3.13 PV
      14. 8.3.14 DIV_ON
      15. 8.3.15 VBAT (Battery Voltage)
      16. 8.3.16 VSUP (Supply Voltage)
      17. 8.3.17 GND (Ground)
      18. 8.3.18 EN or nINT (Enable Input or Interrupt Output)
      19. 8.3.19 nRST (Reset Input and Reset Output)
      20. 8.3.20 VCC (Supply Output)
      21. 8.3.21 VBAT Voltage Divider
      22. 8.3.22 Protection Features
        1. 8.3.22.1  Sleep Wake Error (SWE) Timer
        2. 8.3.22.2  Device Reset
        3. 8.3.22.3  TXD Dominant Time Out (DTO)
        4. 8.3.22.4  Bus Stuck Dominant System Fault: False Wake Up Lockout
        5. 8.3.22.5  Thermal Shutdown
        6. 8.3.22.6  Under-voltage on VSUP
        7. 8.3.22.7  Unpowered Device and LIN Bus
        8. 8.3.22.8  Floating Pins
        9. 8.3.22.9  VCC Voltage Regulator
          1. 8.3.22.9.1 Under or Over Voltage and Short Circuit
          2. 8.3.22.9.2 Output Capacitance Selection
          3. 8.3.22.9.3 Low-Voltage Tracking
          4. 8.3.22.9.4 Power Supply Recommendation
        10. 8.3.22.10 Watchdog
          1. 8.3.22.10.1 Watchdog in Pin Control Mode
          2. 8.3.22.10.2 Watchdog in SPI Control Mode
          3. 8.3.22.10.3 Watchdog Error Counter
          4. 8.3.22.10.4 Pin Control Mode
          5. 8.3.22.10.5 SPI Control Programming
          6. 8.3.22.10.6 Watchdog Register Relationship
          7. 8.3.22.10.7 Watchdog Timing
      23. 8.3.23 Channel Expansion
        1. 8.3.23.1 Channel Expansion for LIN
        2. 8.3.23.2 Channel Expansion for CAN Transceiver
    4. 8.4 Device Functional Modes
      1. 8.4.1 Init Mode
      2. 8.4.2 Normal Mode
      3. 8.4.3 Fast Mode
      4. 8.4.4 Sleep Mode
      5. 8.4.5 Standby Mode
      6. 8.4.6 Restart Mode
        1. 8.4.6.1 Restart Counter
        2. 8.4.6.2 nRST Behavior in Restart Mode
      7. 8.4.7 Fail-safe Mode
      8. 8.4.8 Wake Up Events
        1. 8.4.8.1 Wake Up Request (RXD)
        2. 8.4.8.2 Local Wake Up (LWU) via WAKE Terminal
          1. 8.4.8.2.1 Static WAKE
          2. 8.4.8.2.2 Cyclic Sense Wake
      9. 8.4.9 Mode Transitions
    5. 8.5 Programming
      1. 8.5.1 SPI Communication
        1. 8.5.1.1 Cyclic Redundancy Check
        2. 8.5.1.2 Chip Select Not (nCS)
        3. 8.5.1.3 Serial Clock Input (CLK)
        4. 8.5.1.4 Serial Data Input (SDI)
        5. 8.5.1.5 Serial Data Output (SDO)
    6. 8.6 Registers
      1. 8.6.1  DEVICE_ID_y Register (Address = 0h + formula) [reset = 0h]
      2. 8.6.2  REV_ID_MAJOR Register (Address = 8h) [reset = 01h]
      3. 8.6.3  REV_ID_MINOR Register (Address = 9h) [reset = 0h]
      4. 8.6.4  CRC_CNTL Register (Address = Ah) [reset = 0h]
      5. 8.6.5  CRC_POLY_SET (Address = Bh) [reset = 00h]
      6. 8.6.6  Scratch_Pad_SPI Register (Address = Fh) [reset = 0h]
      7. 8.6.7  WAKE_PIN_CONFIG1 Register (Address = 11h) [reset = 04h]
      8. 8.6.8  WAKE_PIN_CONFIG2 Register (Address = 12h) [reset = 2h]
      9. 8.6.9  WD_CONFIG_1 Register (Address = 13h) [reset = 90h]
      10. 8.6.10 WD_CONFIG_2 Register (Address = 14h) [reset = 02h]
      11. 8.6.11 WD_INPUT_TRIG Register (Address = 15h) [reset = 0h]
      12. 8.6.12 WD_RST_PULSE Register (Address = 16h) [reset = 40h]
      13. 8.6.13 FSM_CONFIG Register (Address = 17h) [reset = 0h]
      14. 8.6.14 FSM_CNTR Register (Address = 18h) [reset = 0h]
      15. 8.6.15 DEVICE_RST Register (Address = 19h) [reset = 0h]
      16. 8.6.16 DEVICE_CONFIG (Address = 1Ah) [reset = 80h]
      17. 8.6.17 DEVICE_CONFIG2 (Address = 1Bh) [reset = 0h]
      18. 8.6.18 SWE_TIMER (Address = 1Ch) [reset = 30h]
      19. 8.6.19 LIN_CNTL (Address = 1Dh) [reset = 00h]
      20. 8.6.20 HSS_CNTL (Address = 1Eh) [reset = 0h]
      21. 8.6.21 PWM1_CNTL1 (Address = 1Fh) [reset = 0h]
      22. 8.6.22 PWM1_CNTL2 (Address = 20h) [reset = 0h]
      23. 8.6.23 PWM1_CNTL3 (Address = 21h) [reset = 00h]
      24. 8.6.24 PWM2_CNTL1 (Address = 22h) [reset = 0h]
      25. 8.6.25 PWM2_CNTL2 (Address = 23h) [reset = 0h]
      26. 8.6.26 PWM2_CNTL3 (Address = 24h) [reset = 0h]
      27. 8.6.27 TIMER1_CONFIG (Address = 25h) [reset = 00h]
      28. 8.6.28 TIMER2_CONFIG (Address = 26h) [reset = 00h]
      29. 8.6.29 RSRT_CNTR (Address = 28h) [reset = 40h]
      30. 8.6.30 nRST_CNTL (Address = 29h) [reset = 00h]
      31. 8.6.31 INT_GLOBAL Register (Address = 50h) [reset = A0h]
      32. 8.6.32 INT_1 Register (Address = 51h) [reset = 0h]
      33. 8.6.33 INT_2 Register (Address = 52h) [reset = 40h]
      34. 8.6.34 INT_3 Register (Address 53h) [reset = 0h]
      35. 8.6.35 INT_EN_1 Register (Address = 56h) [reset = B0h]
      36. 8.6.36 INT_EN_2 Register (Address = 57h) [reset = 37h]
      37. 8.6.37 INT_EN_3 Register (Address =58h) [reset = BCh]
      38. 8.6.38 INT_4 Register (Address = 5Ah) [reset = 0h]
      39. 8.6.39 INT_EN_4 Register (Address = 5Eh) [reset = CCh]
      40. 8.6.40 Reserved Registers
  9. Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Device Brownout Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
        1. 9.2.1.1 Normal Mode Application Note
        2. 9.2.1.2 Standby Mode Application Note
        3. 9.2.1.3 TXD Dominant State Timeout Application Note
      2. 9.2.2 Detailed Design Procedures
      3. 9.2.3 Application Curves
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  10. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Related Documentation
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 Support Resources
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 Glossary
  11. 11Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

AC Switching Characteristics

parameters valid over –40℃ ≤ TJ ≤ 150 ℃ range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Device Switching Characteristics
trx_pdr
trx_pdf
Receiver rising/falling propagation delay time (ISO/DIS 17987 Param 31) RRXD = 2.4 kΩ, CRXD = 20 pF (See Figure 7-3, Figure 7-4) 6 µs
trs_sym Symmetry of receiver propagation delay time Receiver rising propagation delay time (ISO/DIS 17987 Param 32) Rising edge with respect to falling edge, (trx_sym = trx_pdf – trx_pdr), RRXD = 2.4 kΩ, CRXD = 20 pF (See Figure 7-3, Figure 7-4) –2 2 µs
tLINBUS LIN wakeup time (minimum dominant time on LIN bus for wakeup) See Figure 7-6, Figure 8-11 and Figure 8-12 25 100 150 µs
tCLEAR Time to clear false wakeup prevention logic if LIN bus had a bus stuck dominant fault (recessive time on LIN bus to clear bus stuck dominant fault) See Figure 8-12 10 60 µs
tTXD_DTO Dominant state time out 20 45 80 ms
tEN Enable pin deglitch time Time enable pin state change before initiating mode change or sampling TXD pin 3 12 µs
tMODE_CHANGE Mode change delay time Time to change from normal mode to sleep mode through EN pin: See Figure 7-5 100 µs
tDETECT Time to detect Pin vs SPI and I/O voltage level at power up(1) Time from coming out of UVCC and device determines these states 2 µs
tDET_INH Time to detect which output INH or WKRQ at power up Time from coming out of UVCC and device determines these states 25 µs
tNOMINIT Normal mode initialization time Time for normal mode to initialize and data on RXD pin to be valid, includes tMODE_CHANGE for standby mode to normal mode See Figure 7-5 45 µs
tRSTN_act Time required for VCC ≥ UVCC to leave Restart mode VCC ≥ UVCC 1.5 2 2.5 ms
tnRSTIN Input pulse required on the nRST pin to recognize a device reset. 120 µs
tNRST_TOG nRST pin output toggle high to low to high time reg 29h[5] = 0 (Default value in SPI control. Value in pin control except for watchdog failure.) 1.5 2 2.5 ms
reg 29h[5] = 1 (Value in pin control for watchdog failure.) 10 15 20 ms
tINITWD Initial long watchdog window time required to trigger first watchdog input trigger when entering Standby mode or Normal mode WDI input trigger or SPI write command 150 200 ms
tINACT_FS Timer for inactivity coming out of sleep mode and when coming out of failsafe mode to determine if caused event has been cleared (1) Default values and can be programmed to different values in SPI control. 4 5 6 min
tPWRUP Time from VSUP exceeding  UVSUP until INH active VCC > UVCC, INH = VSUP, VCC load of 50 mA @ 22 µF capacitance 3 ms
Time from VSUP exceeding  UVSUP and VCC exceeding  UVCC until WKRQ active VCC > UVCC, WKRQ = VCC, VCC load of 50 mA @ 22 µF capacitance 3 ms
tTOGGLE RXD pulse width when waking from sleep mode register 'h12[2] = 1 5 15 µs
tUVFLTR Undervoltage detection delay time for VCC 3 4 ms
tVSC Short to ground on VCC detection delay time 75 100 130 µs
tLDOON Time LDO is on to determine if a short circuit event is present after a previous uncleared detection 2 3 ms
tMODE_STBY_NOM Standby to normal mode change time based upon SPI write 70 µs
tMODE_NOM_SLP SPI write to go to sleep from normal Time from SPI sleep command where LIN transceiver is off and RXD doesn't reflect the LIN bus 200 µs
tMODE_NOM_STBY SPI write to go to standby from normal mode 70 µs
tWKRQ_SLP Time WKRQ turns on after a wake event when device is in sleep mode Dependent upon LDO turning on and ramp time.  Time provided is based upon 1 µs ramp and LDO being at 2 V.  450 µs
tINH_SLP Time INH turns on after a wake event when device is in sleep mode 210 µs
tINH_NOM_SLP SPI write to go to sleep from normal mode and INH turns off 70 µs
tWK_WIDTH_MIN Minimum WAKE pin pulse width (SPI mode only) (2) (3) (4) Minimum WAKE Pin pulse width Register 8'h11[3:2] = 00b; See Figure 8-46 10 ms
Minimum WAKE Pin pulse width Register  8'h11[3:2] = 01b; See Figure 8-46 20 ms
Minimum WAKE Pin pulse width Register 8'h11[3:2] = 10b; See Figure 8-46 40 ms
Minimum WAKE Pin pulse width Register 8'h11[3:2] = 11b; See Figure 8-46 80 ms
tWK_WIDTH_INVALID Maximum Pulse width that is considered invalid (SPI mode only) (2) (3) Maximum WAKE Pin pulse width that is considered invalid  Register 8'h11[3:2] = 00b; See Figure 8-46 5 ms
Maximum WAKE Pin pulse width that is considered invalid Register 8'h113:2] = 01b; See Figure 8-46 10 ms
Maximum WAKE Pin pulse width that is considered invalid Register 8'h11[3:2] = 10b; See Figure 8-46 20 ms
Maximum WAKE Pin pulse width that is considered invalid Register 8'h11[3:2] = 11b; See Figure 8-46 40 ms
tWK_WIDTH_MAX Maximum WAKE pin pulse width to be considered valid (SPI mode only) (2) Maximum WAKE Pin pulse window Register 8'h11[1:0] = 00b; See Figure 8-46 750 950 ms
Maximum WAKE Pin pulse window  Register 8'h11[1:0] = 01b; See Figure 8-46 1000 1250 ms
Maximum WAKE Pin pulse window Register 8'h11[1:0] = 10b; See Figure 8-46 1500 1875 ms
Maximum WAKE Pin pulse window  Register 8'h11[1:0] = 11b; See Figure 8-46 2000 2500 ms
tWK_CYC Sampling window for cyclic sensing wake; Standby or Sleep mode; see Figure 8-49 Register 8'h12[5] = 0 10 30 40 µs
Register 8'h12[5] = 1 60 75 90 µs
Fast Mode
DR Data Rate 5.5 V ≤ VSUP ≤ 18 V, RLIN = 500 Ω and CLIN(bus) = 600 pF 200 kbps
trx_pdr
trx_pdf
Receiver rising/falling propagation delay time (ISO/DIS 17987 Param 31) RRXD = 2.4 kΩ, CRXD = 20 pF (See Figure 7-3, Figure 7-4 5 µs
ttxr/f LIN transmitter rise and fall time 5.5 V ≤ VSUP ≤ 18 V, RLIN = 500 Ω and CLIN(bus) = 600 pF, 80%/20% 1.5 µs
tFM_CHANGE Fast mode determination time for entering or leaving Based upon EN and TXD voltage levels 70 90 110 µs
tFMTXD TXD pin pulse width to enter fast mode Pulse must start after tEN and finish before tFM_CHANGE 5 25 µs
SPI Switching Characteristics
fSCK SCK, SPI clock frequency (1) 4 MHz
tSCK SCK, SPI clock period (1) See Figure 7-7 250 ns
tRSCK SCK rise time (1) See Figure 7-7 40 ns
tFSCK SCK fall time (1) See Figure 7-7 40 ns
tSCKH SCK, SPI clock high (1) See Figure 7-7 125 ns
tSCKL SCK, SPI clock low (1) See Figure 7-7 125 ns
tACC First read access time from chip select (1) See Figure 7-7 50 ns
tCSS Chip select setup time (1) See Figure 7-7 100 ns
tCSH Chip select hold time (1) See Figure 7-7 100 ns
tCSD Chip select disable time (1) See Figure 7-7 50 ns
tSISU Data in setup time (1) See Figure 7-7 50 ns
tSIH Data in hold time (1) See Figure 7-7 50 ns
tSOV Data out valid (1) See Figure 7-7 80 ns
tRSO SO rise time (1) See Figure 7-7 40 ns
tFSO SO fall time (1) See Figure 7-7 40 ns
Specified by design
This parameter is valid only when register 11h[7:6] = 11b
This is the minimum pulse width for a WAKE pin input that device will detect as a good pulse. Values between the min tWK_WIDTH_MIN
and max tWK_WIDTH_INVALID is indeterminant and may or may not be considered valid.
This parameter is set based upon the programmed value for tWK_WIDTH_INVALID register 11h[3:2]