8.3.1 High-Speed Side Receiver Jitter Tolerance

The peak-to-peak total jitter tolerance for the RP3 receiver is 0.65 UI. This total jitter is composed of three components; deterministic jitter, random jitter, and an additional sinusoidal jitter.

The deterministic jitter tolerance is 0.37 UI minimum. The sum of deterministic and random jitter is 0.55 UI minimum. The additional sinusoidal jitter which the receiver must tolerate will have frequencies and amplitudes conforming to the mask presented in the Figure 9 and Table 1.

Figure 9. OBSAI Sinusoidal Jitter Mask

8.3.2 Lane Alignment Scheme

Lower rate multi-lane serial signals per channel must be byte aligned and lane aligned such that high-speed multiplexing (proper reconstruction of higher rate signal) is possible. For that reason, the TLK10002 implements a special lane alignment scheme on the low-speed (LS) side.

During lane alignment, a proprietary pattern (or a custom comma compliant data stream) is sent by the LS transmitter to the LS receiver on each active lane. This pattern allows the LS receiver to both delineate byte boundaries within a lower speed lane and align bytes across the lanes (2 or 4) such that the original higher rate data ordering is restored.

Lane alignment completes successfully when the LS receiver asserts a Link Status OK signal monitored by the LS transmitter on the link partner device such as an FPGA. The TLK10002 sends out the Link Status OK signals through the LS_OK_OUT_A/B output pins, and monitors the Link Status OK signals from the link partner device through the LS_OK_IN_A/B input pins. If the link partner device does not need the TLK10002 Lane Align Master (LAM) to send proprietary lane alignment pattern, LS_OK_IN_A/B can be tied high on the application board.

The lane alignment scheme is activated under any of the following conditions:

• Device/System power up (after configuration/provisioning)
• Loss of channel synchronization assertion on any enabled LS lane
• Loss of signal assertion on any enabled LS lane
• LS SERDES PLL Lock indication deassertion
• After device configuration change
• After software determined LS 8B/10B decoder error rate threshold exceeded
• After device reset is deasserted
• Anytime the LS receiver deasserts Link Status OK.
• Presence of reoccurring higher level / protocol framing errors

The block diagram of the lane alignment scheme is shown in Figure 10.

Figure 10. Block Diagram of the Lane Alignment Scheme

8.3.3 Lane Alignment Components

• Lane Alignment Master (LAM)
  • Responsible for generating proprietary LS lane alignment initialization pattern
  • Resides in the TLK10002 LS receiver (one instance in Channel A, one instance in Channel B)
    • Responsible for bringing up LS receive link for the data sent from the TLK10002 to a link partner device
    • Monitors the LS_OK_IN_A/B pins for Link Status OK signals sent from the Lane Alignment Slave (LAS) of the link partner device
  • Resides in the link partner device (one instance in Channel A, one instance in Channel B)
    • Responsible for bringing up LS transmit link for the data sent from the link partner device to the TLK10002
    • Monitors the Link Status OK signals sent from the LS_OK_OUT_A/B pins of the Lane Alignment Slave (LAS) of the TLK10002
• Lane Alignment Slave (LAS)
  • Responsible for monitoring the LS lane alignment initialization pattern
  • Performs channel synchronization per lane (2 or 4 lanes) through byte rotation
  • Performs lane alignment and realignment of bytes across lanes
  • Resides in the TLK10002 LS receiver (one instance in Channel A, one instance in Channel B)
    • Generates the Link Status OK signal for the LAM on the link partner device
  • Resides in the link partner device (one instance in Channel A, one instance in Channel B)
    • Generates the Link Status OK signal for the LAM on the TLK10002 device.

8.3.4 Lane Alignment Operation

During lane alignment, the LS transmitter (LAM) sends a repeating pattern of 49 characters (control + data) simultaneously across all enabled LS lanes. These simultaneous streams are then encoded by 8B/10B encoders in parallel. The proprietary lane alignment pattern consists of the following characters:

/K28.5/ (CTL=1, Data=0xBC)

Repeat the following sequence of 12 characters four times:

/D30.5/ (CTL=0, Data=0xBE)
/D23.6/ (CTL=0, Data=0xD7)
/D3.1/ (CTL=0, Data=0x23)
/D7.2/ (CTL=0, Data=0x47)
/D11.3/ (CTL=0, Data=0x6B)
/D15.4/ (CTL=0, Data=0x8F)
/D19.5/ (CTL=0, Data=0xB3)
/D20.0/ (CTL=0, Data=0x14)
/D30.2/ (CTL=0, Data=0x5E)
/D27.7/ (CTL=0, Data=0xFB)
/D21.1/ (CTL=0, Data=0x35)
/D25.2/ (CTL=0, Data=0x59)

The above 49-character sequence is repeated until LS_OK_IN_A/B is asserted. Once LS_OK_IN_A/B is asserted, the LAM resumes transmitting traffic received from the high speed side SERDES immediately.

The TLK10002 performs lane alignment across the lanes similar in fashion to the IEEE 802.3ae-2002 (XAUI) specification. XAUI only operates across 4 lanes while LAS operates with 2 or 4 lanes. The lane alignment state machine is shown in Figure 11. The comma (K28.5) character is used for lane to lane alignment instead of XAUI’s /A/ character.

Lane alignment checking is not performed by the LAS after lane alignment is achieved. After LAM detects that the LS_OK_IN_A/B signal is asserted, normal system traffic is carried instead of the proprietary lane alignment pattern.

Channel Synchronization is performed during lane alignment and normal system operation.

Figure 11. Lane Alignment State Machine

8.3.5 Channel Synchronization

The TLK10002 performs channel synchronization per lane as per IEEE802.3-2002 Figure 36–9 Synchronization state diagram and as shown in the flowchart of Figure 12.

Figure 12. Channel Synchronization Flowchart

8.3.6 Line Rate, SERDES PLL Settings, and Reference Clock Selection

The TLK10002 includes internal low-jitter high quality oscillators that are used as frequency multipliers for the low-speed and high-speed SERDES and other internal circuits of the device. Specific MDIO registers are available for SERDES rate and PLL multiplier selection to match line rates and reference clock (REFCLK0/1) frequencies for various applications.

The external differential reference clock has a large operating frequency range allowing support for many different applications. The reference clock frequency must be within 200 PPM of the incoming serial data rate (±100 PPM of nominal data rate), and have less than 40 ps of jitter. Table 2 shows a summary of line rates and reference clock frequencies used for CPRI/OBSAI for the 1:1, 2:1, and 4:1 operation modes.

Table 2, Table 3, and Table 4 indicate two possible reference clock frequencies for CPRI/OBSAI applications: 153.6 MHz and 122.88 MHz, which can be used based on the application preference. The SERDES PLL Multiplier (MPY) has been given for each reference clock frequency respectively. For each channel, the low-speed side and the high-speed side SERDES use the same reference clock frequency. Note that Channel A and B are independent and their application rates and references clocks are separate.

For other line rates not shown in Table 3 and Table 4, valid reference clock frequencies can be selected with the help of the information provided in Table 5 and Table 6 for the low-speed side and high-speed side SERDES. The reference clock frequency has to be the same for the two SERDES and must be within the specified valid ranges for different PLL multipliers.

For example, in the 2:1 operation mode, if the low-speed side line rate is 1.987 Gbps, the high-speed side line rate is 3.974 Gbps. The following steps can be taken to make a reference clock frequency selection:

1. Determine the appropriate SERDES rate modes that support the required line rates. Table 5 shows that the 1.987 Gbps line rate on the low-speed side is only supported in the half rate mode (RateScale = 1). Table 6 shows that the 3.974 Gbps line rate on the high-speed side is only supported in the half rate mode (RateScale = 0.5).
2. For each SERDES side, and for all available PLL multipliers (MPY), compute the corresponding reference clock frequencies using the formula:

Reference Clock Frequency = (LineRate x RateScale)/MPY

The computed reference clock frequencies are shown in Table 7 along with the valid minimum and maximum frequency values.

3. Mark all the common frequencies that appear on both SERDES sides. Note and discard all those that fall outside the allowed range. In this example, the common frequencies are highlighted in Table 7.
4. Select any of the remaining marked common reference clock frequencies. Higher reference clock frequencies are generally preferred. In this example, any of the reference clock frequencies in Table 7 can be selected: 397.4 MHz, 331.167 MHz, 248.375 MHz, 198.7 MHz, 165.583 MHz, 158.96 MHz, and 132.467 MHz.

8.3.7 Clocking Architecture

A simplified clocking architecture for the TLK10002 is captured in Figure 13. Each channel (Channel A or Channel B) has an option of operating with a differential reference clock provided either on pins REFCLK0P/N or REFCLK1P/N. The choice is made either through MDIO or through REFCLKA_SEL and REFCLKB_SEL pins. The reference clock frequencies for those two clock inputs can be different as long as they fall under the valid ranges shown in Table 6. For each channel, the low-speed side SERDES, high-speed side SERDES and the associated part of the digital core operate from the same reference clock.

The clock and data recovery (CDR) function of the high-speed side receiver recovers the clock from the incoming serial data. The high-speed side SERDES makes available two versions of clocks for further processing:

1. HS_RXBCLK_A/B: recovered byte clock synchronous with incoming serial data and with a frequency matching the incoming line rate divided by 20.
2. VCO_CLOCK_A/B_DIV2: VCO frequency divided by 2. (VCO frequency = REFCLK x PLL Multiplier).

The above-mentioned clocks can be output through the differential pins, CLKOUTAP/N and CLKOUTBP/N, with optional frequency division ratios of 1, 2, 4, 5, 8, 10, 16, 20, or 25. The clock output options are software controlled through the MDIO interface register bits 1.3:2, and 1.7:4. The maximum CLKOUT frequency is 500 MHz.

Figure 13. Clocking Architecture

8.3.8 Loopback Modes

The TLK10002 provides two high-speed side (remote) and two low-speed side (local) loopback modes for self-test and system diagnostic purposes. The details of those loopback modes are discussed below.

8.3.9 Deep Remote Loopback

The deep remote loopback is as shown Figure 14 for Channel A. The configuration is the same for Channel B. The loopback mode is activated and configured through the MDIO interface. In this loopback mode, the data is accepted on the high-speed side receive SERDES pins (HSRXAP/N or HSRXBP/N), traverses the entire receive data path excluding the CML driver and receive sense amps on the low-speed side SERDES, returned through the entire transmit data path and sent out through the high-speed side transmit SERDES pins (HSTXAP/N or HSTXBP/N).

The low-speed side outputs on OUTA*P/N or OUTB*P/N pins are still available for monitoring. See MDIO register bit 6.7 in Table 21 for more information. The OUTA*P/N and OUTB*P/N pins must be correctly terminated.

The link partner connected through INA*P/N or INB*P/N pins must be electrically idle at differential zero with P and N signals at the same voltage. The TLK10002 device needs some time for lane alignment before passing traffic. The LS_OK_IN_A/B signal is ignored as the device is internally listening to the local LS_OK_OUT_A/B.

Figure 14. Deep Remote Loopback

8.3.10 Shallow Remote Loopback and Serial Retime

The shallow remote loopback is as shown in Figure 15 for Channel A. The configuration is the same for Channel B. The loopback mode is activated and configured through the MDIO interface. In this loopback mode, the data is accepted on the high-speed side receive SERDES pins (HSRXAP/N or HSRXBP/N), traverses the receive data path and looped back before the low-speed SERDES, returned through the transmit data path and sent out through the high-speed side transmit SERDES pins (HSTXAP/N or HSTXBP/N).

The low-speed side transmit path SERDES can be optionally enabled or disabled but the PLL needs to be enabled to provide the required clock.

The low-speed side outputs on OUTA*P/N or OUTB*P/N pins are still available for monitoring. The OUTA*P/N and OUTB*P/N pins must be correctly terminated. The TLK10002 device needs some time for lane alignment before passing traffic. The LS_OK_IN_A/B signal is ignored as the device is internally listening to the local LS_OK_OUT_A/B.

This loopback mode can be used for high-speed serial retime operation.

Figure 15. Shallow Remote Loopback

8.3.11 Deep Local Loopback

The deep local loopback mode is as shown in Figure 16 for Channel A. The configuration is the same for Channel B. The loopback mode is activated and configured through the MDIO interface. In this loopback mode, the data is accepted on the low-speed side SERDES pins (INA*P/N or INB*P/N), traverses the entire transmit data path excluding the CML driver, returned through the entire receive data path and sent out through the low-speed side SERDES pins (OUTA*P/N or OUTB*P/N). The TLK10002 device needs some time for lane alignment before passing traffic. The high-speed side outputs on HSTXAP/N or HSTXBP/N pins are available for monitoring.

Figure 16. Deep Local Loopback

8.3.12 Shallow Local Loopback

The shallow local loopback mode is as shown in Figure 17 for Channel A. The configuration is the same for Channel B. The loopback mode is activated and configured through the MDIO interface. In this loopback mode, the data is accepted on the low-speed side SERDES pins (INA x P/N or INB x P/N), traverses the entire transmit data path excluding the high-speed side SERDES, returned through the entire receive data path and sent out through the low-speed side SERDES pins (OUTA x P/N or OUTB x P/N). The TLK10002 device needs some time for lane alignment before passing traffic. The high-speed side outputs on HSTXAP/N or HSTXBP/N pins are available for monitoring.

Figure 17. Shallow Local Loopback

8.3.13 Test Pattern Generation and Verification

The TLK10002 has an extensive suite of built-in test functions to support system diagnostic requirements. Each channel has sets of internal test pattern generators and verifiers.

Several patterns can be selected through the MDIO interface that offer extensive test coverage. The low-speed side supports generation and verification of pseudo-random bit sequence (PRBS) 2⁷-1, 2²³-1, and 2³¹-1 patterns. In addition to those PRBS patterns, the high-speed side supports High-frequency (HF), Low-frequency (LF), Mixed-frequency (MF), and continuous random test pattern (CRPAT) long/short pattern generation and verification as defined in Annex 48A of the IEEE Standard 802.3ae-2002. Use of CRPAT verifier requires checking TPsync (MDIO register bit F.15).

The TLK10002 provides two pins: PRBSEN and PRBS_PASS, for additional and easy control and monitoring of PRBS pattern generation and verification. When the PRBSEN is asserted high, the internal PRBS generator and verifier circuits are enabled on both transmit and receive data paths on high-speed and low-speed sides of both channels. This signal is logically OR’d with an MDIO register bits B.7:6 and B.13:12.

PRBS 2³¹-1 is selected by default, and can be changed through MDIO.

When PRBS test is enabled (PRBSEN=1):

• PRBS_PASS=1 indicates that PRBS pattern reception is error free.
• PRBS_PASS=0 indicates that a PRBS error is detected. The channel, the side (high speed or low speed), and the lane (for low-speed side) that this signal refers to is chosen through MDIO register bit 0.3:0.

8.3.14 Latency Measurement Function

The TLK10002 includes a latency measurement function to support CPRI and OBSAI base station applications. There are two start and two stop locations for the latency counter as shown in Figure 18 for Channel A. The start and stop locations are selectable through MDIO register bits 0x16.7 and 0x16.6 respectively. The elapsed time from a comma detected at an assigned counter start location of a particular channel to a comma detected at an assigned counter stop location of the same channel is measured and reported through the MDIO interface. The function operates on one channel at a time. The following three control characters (containing commas) are monitored:

1. K28.1 (control = 1, data = 0x3C)
2. K28.5 (control = 1, data = 0xBC)
3. K28.7 (control = 1, data = 0xFC).

The first comma found at the assigned counter start location starts up the latency counter. The first comma detected at the assigned counter stop location stops the latency counter. The 20-bit latency counter result of this measurement is readable through the MDIO interface through register bits 0x17.3:0 and 0x18.15:0. The accuracy of the measurement is a function of the serial bit rate at which the channel being measured is operating. The register will return a value of 0xFFFF if the duration between transmit and receive comma detection exceeds the depth of the counter. Only one measurement value is stored internally until the 20-bit results counter is read. The counter will return zero in cases where a transmit comma was never detected (indicating the results counter never began counting).

Figure 18. Location of TX and RX Comma Character Detection (Only Channel A Shown)

In high-speed side SERDES full rate mode, the latency measurement function runs off of an internal clock whose rate is equal to the transmit serial bit rate divided by 8. In half rate mode, the latency measurement function runs off of an internal clock whose rate is equal to the serial bit rate divided by 4. In quarter rate mode, the latency measurement function runs off of an internal clock whose rate is equal to the serial bit rate divided by 2. In eighth rate mode, the latency measurement function runs off of a clock whose rate is equal to the serial bit rate.

The latency measurement does not include the low-speed side transmit SERDES blocks contribution as well as part of the channel synchronization block. The latency introduced by these blocks can be estimated to be up to (18 + 10) x N high-speed side unit intervals (UIs), where the multiplex factor N is equal to 2 (in 2:1 mode) or 4 (in 4:1 mode). The latency measurement also doesn’t account for the low-speed side receive SERDES contribution which is estimated to be up to 20 x N high-speed side UIs. The latency contributions of various sections of the TLK10002 device are shown in Figure 17. Overall, the transmit data path full rate latency contribution is estimated to be between 462UI and 602UI for the 2:1 mode, and between 798UI and 1058UI for the 4:1 mode. The respective numbers for the receive data path are between 300UI and 403UI for the 2:1 mode and between 440UI and 623UI for the 4:1 mode.

The latency measurement accuracy in all cases is equal to plus or minus one latency measurement clock period. The measurement clock can be divided down if a longer duration measurement is required, in which case the accuracy of the measurement is accordingly reduced. The high-speed latency measurement clock is divided by either 1, 2, 4, or 8 via register 0x16 bits 5:4. The measurement clock used is always selected by the channel under test. The high-speed latency measurement clock may only be used when operating at one of the serial rates specified in the CPRI/OBSAI specifications. It is also possible to run the latency measurement function off of the recovered byte clock for the channel under test (and gives a latency measurement clock frequency equal to the serial bit rate divided by 20) through register 0x16 bit 2 (where the register 0x16 bits 5:4 divider value setting is ignored).

The accuracy for the standard based CPRI/OBSAI application rates is shown in Table 8, and assumes the latency measurement clock is not divided down per user selection (division is required to measure a duration greater than 682 µs). For each division of two in the measurement clock, the accuracy is also reduced by a factor of two.

To use the latency measurement feature, follow this procedure:

1. Provision stopwatch clock frequency (divide by N), channel select, and start or stop location through the LATENCY_MEASURE_CONTROL register (0x16) and enable the stopwatch clock. In choosing a divider, note that the frequency of the divided clock must not be slower than the internal high speed byte clock.
2. Read status register 18.15:0 to clear and reset delay stopwatch.
3. Send comma pattern (after lane alignment has been achieved and the link status is OK).
4. Poll bit 17.4 until it is asserted.
5. Read the start and stop comma location and the lane align pointer values indicating relative skew among the lanes of the selected channel. These may need to be processed together with the stopwatch counter values for more accurate latency analysis.
6. Read counter status values. The four MSB in bits 17.3:0 should be read first, followed by the LSBs in 18.15:0. If the value is 0, then the comma was never detected. If the value is at its maximum, the delay was too long for the counter’s range. If this happens, decrease the measurement clock frequency and repeat the measurement.
7. Once the lower 16 bits at 18.15:0 are read, the delay stopwatch is reset and 17.4 is cleared. The comma location latch registers are cleared too. To do a new measurement, start again from step (3) for the same channel and from step (1) if a different channel is desired.
8. Take the counter value and multiply it with the latency clock period divided by 2. This will provide the absolute latency period.

NOTE:

Latency numbers represent no external skew between lanes. External lane skew will increase overall latency. TX Datapath latency includes 20xN UI of variance due to deserialization and channel sync.

Figure 19. Latency Variance and Contributions (Only Channel A Shown)

8.3.15 Power-Down Mode

The TLK10002 can be put in power down either through device inputs pins or through MDIO control register (1.15).

PDTRXA_N: Active low, powers down channel A.
PDTRXB_N: Active low, powers down channel B.

The MDIO management serial interface remains operational when in register-based, power-down mode (1.15 asserted for both channels), but status bits may not be valid since the clocks are disabled. The low-speed side and high-speed side SERDES outputs are high impedance when in power-down mode. See the detailed per pin description for the behavior of each device I/O signal during pin-based and register-based power down.

8.3.16 High Speed CML Output

The high-speed data output driver is implemented using Current Mode Logic (CML) with integrated pullup resistors, requiring no external components. The transmit outputs must be AC-coupled.

Figure 20. Example of High-Speed I/O AC-Coupled Mode (Channel A HS Side is Shown)

Current Mode Logic (CML) drivers often require external components. The disadvantage of the external component is a limited edge rate due to package and line parasitic. The CML driver on TLK10002 has on-chip 50-Ω termination resistors terminated to VDDT, providing optimum performance for increased speed requirements. The transmitter output driver is highly configurable allowing output amplitude and de-emphasis to be tuned to a channel's individual requirements. Software programmability allows for very flexible output amplitude control. Only AC-coupled output mode is supported.

When transmitting data across long lengths of PCB trace or cable, the high-frequency content of the signal is attenuated due to the skin effect of the media. This causes a smearing of the data eye when viewed on an oscilloscope. The net result is reduced timing margins for the receiver and clock recovery circuits. In order to provide equalization for the high frequency loss, 3-tap finite impulse response (FIR) transmit de-emphasis is implemented. A highly configurable output driver maximizes flexibility in the end system by allowing de-emphasis and output amplitude to be tuned to a channel’s individual requirements. Output swing is controlled via MDIO.

Figure 2 illustrates the output waveform flexibility. The level of de-emphasis is programmable through the MDIO interface through control registers (5.7:4 and 5.12:8) through pre-cursor and post-cursor settings. Users can control the strength of the de-emphasis to optimize for a specific system requirement.

8.3.17 High Speed Receiver

The high-speed receiver is differential CML with internal termination resistors. The receiver requires AC coupling. The termination impedances of the receivers are configured as 100 Ω with the center tap weakly tied to 0.8 × VDDT with a capacitor to create an AC ground.

TLK10002 serial receivers incorporate adaptive equalizers. This circuit compensates for channel insertion loss by amplifying the high frequency components of the signal, reducing inter-symbol interference. Equalization can be enabled or disabled through register settings. Both the gain and bandwidth of the equalizer are controlled by the receiver equalization logic.

8.3.18 Loss of Signal Indication (LOS)

Loss of input signal detection is based on the voltage level of each serial input signal INA x P/N, INB x P/N, HSRXAP/N, and HSRXBP/N. When LOS indication is enabled and a channel's differential serial receive input level is < 75 mVpp, that channel's respective LOS indicator (LOSA or LOSB) is asserted (high true). If the input signal is >150 mVpp, the LOS indicator is deasserted (low false). Outside of these ranges, the LOS indication is undefined. The LOS indicators are also directly readable through the MDIO interface.

The following additional critical status conditions can be combined with the loss of signal condition enabling additional real-time status signal visibility on the LOSA and LOSB outputs per channel:

1. Loss of Channel Synchronization Status – Logically OR’d with LOS condition(s) when enabled. Loss of channel synchronization can be optionally logically OR’d (disabled by default) with the internally generated LOS condition (per channel).
2. Loss of PLL Lock Status on LS and HS sides – Logically OR’d with LOS condition(s) when enabled. The internal PLL loss of lock status bit is optionally OR’d (disabled by default) with the other internally generated loss of signal conditions (per channel).
3. Receive 8B/10B Decode Error (Invalid Code Word or Running Disparity Error) – Logically OR’d with LOS condition(s) when enabled. The occurrence of an 8B/10B decode error (invalid code word or disparity error) is optionally OR’d (disabled by default) with the other internally generated loss of signal conditions (per channel).
4. AGCLOCK (Active Gain Control Currently Locked) – Inverted and Logically OR’d with LOS condition(s) when enabled. HS RX SERDES adaptive gain control unlocked indication is optionally OR’d (disabled by default) with the other internally generated loss of signal conditions (per channel).
5. AZDONE (Auto Zero Calibration Done) – Inverted and Logically OR’d with LOS conditions(s) when enabled. HS RX SERDES auto-zero not done indication is optionally OR’d (disabled by default) with the other internally generated loss of signal conditions (per channel).

Figure 21 shows the detailed implementation of the LOSA signal along with the associated MDIO control registers.

NOTE:

LOSA is asserted (driven high) during a failing condition, and deasserted (driven low) otherwise. Any combinations of status signals may be enabled onto LOSA/B on MDIO register bits indicated above. LOSB circuit is similar.

Figure 21. LOSA – Logic Circuit Implementation

8.3.19 MDIO Management Interface

The TLK10002 supports the Management Data Input/Output (MDIO) Interface as defined in Clause 22 of the IEEE 802.3 Ethernet specification. The MDIO allows register-based management and control of the serial links.

The MDIO Interface consists of a bidirectional data path (MDIO) and a clock reference (MDC). The port address is determined by control pins PRTAD[4:0] as described in Pin Configuration and Functions.

In Clause 22, the top 4 control pins PRTAD[4:1] determine the device port address. In this mode the 2 individual channels in TLK10002 are classified as 2 different ports. So for any PRTAD[4:1] value there are 2 ports per TLK10002.

TLK10002 responds if the 4 MSB’s of PHY address field on MDIO protocol (PA[4:1]) matches PRTAD[4:1]. The LSB of PHY address field (PA[0]) determines which channel/port within TLK10002 to respond to.

If PA[0] = 1'b0, TLK10002 Channel A will respond.

If PA[0] = 1'b1, TLK10002 Channel B responds.

Write transactions which address an invalid register or device, or a read-only register, are ignored. Read transactions which address an invalid register return a 0.

8.3.20 MDIO Protocol Timing

The Clause 22 timing required to read from the internal registers is shown in Figure 22. The Clause 22 timing required to write to the internal registers is shown in Figure 23.

1. Note that the 1 in the Turn Around section is externally pulled up, and driven to Z by TLK10002.

Figure 22. CL22 - Management Interface Read Timing1

Figure 23. CL22 - Management Interface Write Timing

8.3.21 Clause 22 Indirect Addressing

The TLK10002 Register space is divided into two register groups. One register group can be addressed directly through Clause 22, and one register group can be addressed indirectly through Clause 22. The register group which can be addressed through Clause 22 indirectly is implemented in the vendor specific register space (16’h8000 onwards). Due to Clause 22 register space limitations, an indirect addressing method is implemented so that this extended register space can be accessed through Clause 22. To access this register space (16’h8000 onwards), an address control register (Reg 30, 5’h1E) must be written with the register address followed by a read or write transaction to address data register (Reg 31, 5’h1F) to access the contents of the address specified in address control register.

Figure 24 and Figure 25 illustrate an example write transaction to Register 16’h8000 using indirect addressing in Clause 22.

Figure 24. CL22 – Indirect Address Method – Address Write

Figure 25. CL22 - Indirect Address Method – Data Write

Figure 26 and Figure 27 illustrate an example read transaction to read contents of Register 16’h8000 using indirect addressing in Clause 22.

Figure 26. CL22 - Indirect Address Method – Address Write

1. Note that the 1 in the Turn Around section is externally pulled up, and driven to Zero by TLK10002.

Figure 27. CL22 - Indirect Address Method – Data Read1

The IEEE 802.3 Clause 22 specification defines many of the registers, and additional registers have been implemented for expanded functionality.

8.4.1 Transmit (Low Speed to High Speed) Data Path

The TLK10002 transmit data path with the device configured to operate in the normal transceiver (mission) mode is as shown in Figure 28 and Figure 29. In this mode, 8B/10B encoded serial data (IN*P/N) in 2 or 4 lanes is received by the low-speed side SERDES and deserialized into 10-bit parallel data for each lane. The data in each individual lane is then byte aligned (channel synchronized) and then 8B/10B decoded into 8-bit parallel data for each lane. The lane data is then lane aligned by the Lane Alignment Slave. 32-bits of lane aligned parallel data is subsequently fed into a transmit FIFO which delivers it to an 8B/10B encoder, 16 data bits at a time. The resulting 20-bit 8B/10B encoded parallel data is handed to the high-speed side SERDES for serialization and output through the HSTX*P/N pins. This process is exactly the same for both Channel A and Channel B.

Figure 28. Transmit Data Path for the 2:1 Mode

Figure 29. Transmit Data Path for the 4:1 Mode

8.4.2 Receive (High Speed to Low Speed) Data Path

With the device configured to operate in the normal transceiver (mission) mode, the receive data path is as shown in Figure 31. 8B/10B encoded serial data (HSRX*P/N) is received by the high-speed side SERDES and deserialized into 20-bit parallel data. The data is then byte aligned, 8B/10B decoded into 16-bit parallel data, and then delivered to a receive FIFO. The receive FIFO in turn delivers 32-bit parallel data to the Lane Alignment Master which splits the data into the same number of lanes as configured on the transmit data path. The lane data is then 8B/10B encoded and the resulting 10-bit parallel data for each lane is fed into the low-speed side SERDES for serialization and output through the OUT*P/N pins. This process is exactly the same for both Channel A and Channel B.

Figure 30. Receive Data Path for the 2:1 Modes

Figure 31. Receive Data Path for the 4:1 Modes

8.4.3 1:1 Retime Mode

In the 1:1 Retime mode shown in Figure 32, the lane alignment and 8B/10B encoding/decoding blocks are not included in the data path. In the transmit data path, low-speed side data received on the IN*0P/N pins is deserialized, phase corrected by the transmit FIFO, and serialized again before it is output through the HSTX*P/N pins. In the receive data path, high-speed side data received on the HSRX*P/N pins is deserialized, phase corrected by the receive FIFO, and serialized again before it is output through the OUT*0P/N pins. All SERDES controls such as preemphasis, swing, equalizer in registers HS/LS_SERDES_CONTROL_*, and loopback modes are supported as in the 2:1 and 4:1 modes.

Figure 32. 1:1 Mode Transmit and Receive Data Paths

The 1:1 mode only uses lane 0 on the low-speed side and is enabled by setting TX_MODE_SEL and RX_MODE_SEL to 1 (1.13:12 = 2'b11) per channel. The maximum data rate supported in the 1:1 mode is 5Gbps. The minimum data rate supported is 1Gbps. LS_OK_OUT_* status pin must be ignored. If needed for monitoring the link status, only PLL lock and LOS are relevant.

The latency measurement function is not supported in the 1:1 mode. In the 1:1 mode, the High-Speed Channel Sync (register F.10) and Low-Speed Lane 0 Channel Sync (register 15.8) are not part of their respective data paths.

In the 1:1 mode, the data path supports non-8B/10B encoded data, for example, PRBS.

In this mode, any registers related to lane 1, 2, or 3 are not used or do not apply. In addition, the following registers do not apply:

• 1.11:8
• 9.8:4
• C, D, 15(except 15.10), 16, 17, 18, 1D
• F.14, F.10, F.8, F.3:2

8.5.1 Power Sequencing Guidelines

The TLK10002 allows either the core or I/O power supply to be powered up for an indefinite period of time while the other supply is not powered up, if all of the following conditions are met:

1. All maximum ratings and recommended operating conditions are followed.
2. Bus contention while 1.5-V or 1.8-V power is applied (> 0 V) must be limited to 100 hours over the projected lifetime of the device.
3. Junction temperature is less than 105°C during device operation. Note: Voltage stress up to the absolute maximum voltage values for up to 100 hours of lifetime operation at a junction temperature of 105°C or lower will minimally impact reliability.

The TLK10002 inputs are not failsafe (that is, cannot be driven with the I/O power disabled). TLK10002 inputs must not be driven high until their associated power supplies are active.

Table 9. GLOBAL_CONTROL_1 — Address: 0x00 Default: 0x0600

Table 10. CHANNEL_CONTROL_1 — Address: 0x01 Default: 0x0300

Table 11. HS_SERDES_CONTROL_1 — Address: 0x02 Default: 0x811D

Table 12. High-Speed Side SERDES PLL Multiplier Control

Table 13. HS_ SERDES_CONTROL_2 — Address: 0x03 Default: 0xA444

Table 14. High-Speed Side SERDES AC Mode Output Swing Control

Table 15. HS_ SERDES_CONTROL_3 — Address: 0x04 Default: 0xB820

Table 16. High-Speed Side SERDES Cursor Reduction Factor Weights

Table 17. HS_ SERDES_CONTROL_4— Address: 0x05 Default: 0x2000

Table 18. High-Speed Side SERDES Post-Cursor1 Transmit Tap Weights

Table 19. High-Speed Side SERDES Post-Cursor2 Transmit Tap Weights

Table 20. High-Speed Side SERDES Pre-Cursor Transmit Tap Weights

Table 21. LS_ SERDES_CONTROL_1 — Address: 0x06 Default: 0xF115

Table 22. Low-Speed Side SERDES PLL Multiplier Control

Table 23. LS_ SERDES_CONTROL_2 — Address: 0x07 Default: 0xDC04

Table 24. Low-Speed Side SERDES AC Mode Output Swing Control

Table 25. Low-Speed Side SERDES Output De-Emphasis

Table 26. LS_ SERDES_CONTROL — Address: 0x08 Default: 0x0001

Table 27. Low-Speed Side SERDES Equalization

Table 28. HS_OVERLAY_CONTROL — Address: 0x09 Default: 0x0900

Table 29. LS_OVERLAY_CONTROL — Address: 0x0A Default: 0x4000

Table 30. LOOPBACK_TP_CONTROL — Address: 0x0B Default: 0x0700

Table 31. LAS_CONFIG_CONTROL — Address: 0x0C Default: 0x03F0

Table 32. LAS_BER_TMER_CONTROL — Address: 0x0D Default: 0xFFFF

Table 33. RESET_CONTROL — Address: 0x0E Default: 0x0000

Table 34. CHANNEL_STATUS_1 — Address: 0x0F Default: 0x0000

Table 35. HS_ERROR_COUNTER — Address: 0x10 Default: 0xFFFD

Table 36. LS_LN0_ERROR_COUNTER — Address: 0x11 Default: 0xFFFD

Table 37. LS_LN1_ERROR_COUNTER — Address: 0x12 Default: 0xFFFD

Table 38. LS_LN2_ERROR_COUNTER — Address: 0x13 Default: 0xFFFD

Table 39. LS_LN3_ERROR_COUNTER — Address: 0x14 Default: 0xFFFD

Table 40. LAS_STATUS_1 — Address: 0x15 Default: 0x0000

Table 41. LATENCY_MEASURE_CONTROL — Address: 0x16 Default: 0x7F00

Table 42. LATENCY_COUNTER_2 — Address: 0x17 Default: 0x0000

Table 43. LATENCY_COUNTER_1 — Address: 0x18 Default: 0x0000

Table 44. TI_RESERVED_CONTROL_1 — Address: 0x19 Default: 0x0000

Table 45. TI_RESERVED_CONTROL_2 — Address: 0x1A Default: 0x0000

Table 46. TI_RESERVED_STATUS_1 — Address: 0x1B Default: 0x0000

Table 47. MISC_CONTROL_3 — Address: 0x1C Default: 0x3000

Table 48. LAS_STATUS_2 — Address: 0x1D Default: 0x0000

Table 49. EXT_ADDRESS_CONTROL — Address: 0x1E Default: 0x0000

Table 50. EXT_ADDRESS_DATA — Address: 0x1F Default: 0x0000

Table 51. TI_ RESERVED_STATUS_2 — Address: 0x8000 Default: 0x0000

Table 52. TI_RESERVED_STATUS_3 — Address: 0x8001 Default: 0x0000

Table 53. TI_RESERVED_STATUS_4 — Address: 0x8002 Default: 0x0000

Table 54. TI_RESERVED_STATUS_5 — Address: 0x8003 Default: 0x0000

Table 55. TI_RESERVED_STATUS_6 — Address: 0x8004 Default: 0x0000

Table 56. TI_RESERVED_STATUS_7 — Address: 0x8005 Default: 0x0000

Table 57. TI_RESERVED_STATUS_8 — Address: 0x8006 Default: 0x0000

Table 58. TI_RESERVED_STATUS_9 — Address: 0x8007 Default: 0x0000

Table 59. TI_RESERVED_STATUS_10 — Address: 0x8008 Default: 0x0000

Table 60. TI_RESERVED_STATUS_11 — Address: 0x8009 Default: 0x0000

Table 61. TI_RESERVED_STATUS_12 — Address: 0x800A Default: 0x0000