SLLSE75B May   2011  – July 2016 TLK10002

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Description (continued)
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  10-Gbps Power Characteristics - 1.0 V
    6. 7.6  10-Gbps Power Characteristics - 1.5 V
    7. 7.7  10-Gbps Power Characteristics - 1.8 V
    8. 7.8  Transmitter and Receiver Characteristics
    9. 7.9  MDIO Timing Requirements
    10. 7.10 JTAG Timing Requirements
    11. 7.11 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  High-Speed Side Receiver Jitter Tolerance
      2. 8.3.2  Lane Alignment Scheme
      3. 8.3.3  Lane Alignment Components
      4. 8.3.4  Lane Alignment Operation
      5. 8.3.5  Channel Synchronization
      6. 8.3.6  Line Rate, SERDES PLL Settings, and Reference Clock Selection
      7. 8.3.7  Clocking Architecture
      8. 8.3.8  Loopback Modes
      9. 8.3.9  Deep Remote Loopback
      10. 8.3.10 Shallow Remote Loopback and Serial Retime
      11. 8.3.11 Deep Local Loopback
      12. 8.3.12 Shallow Local Loopback
      13. 8.3.13 Test Pattern Generation and Verification
      14. 8.3.14 Latency Measurement Function
      15. 8.3.15 Power-Down Mode
      16. 8.3.16 High Speed CML Output
      17. 8.3.17 High Speed Receiver
      18. 8.3.18 Loss of Signal Indication (LOS)
      19. 8.3.19 MDIO Management Interface
      20. 8.3.20 MDIO Protocol Timing
      21. 8.3.21 Clause 22 Indirect Addressing
    4. 8.4 Device Functional Modes
      1. 8.4.1 Transmit (Low Speed to High Speed) Data Path
      2. 8.4.2 Receive (High Speed to Low Speed) Data Path
      3. 8.4.3 1:1 Retime Mode
    5. 8.5 Programming
      1. 8.5.1 Power Sequencing Guidelines
    6. 8.6 Register Maps
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curve
    3. 9.3 Initialization Setup
      1. 9.3.1 4:1 Mode (9.8304 Gbps on HS Side, 2.4576 Gbps Per Lane on LS Side)
      2. 9.3.2 2:1 Mode (9.8304 Gbps on HS Side, 4.9152 Gbps Per Lane on LS Side, Only Lanes 0 and 1 on LS Side Active)
      3. 9.3.3 1:1 Mode (4.9152 Gbps on HS Side, 4.9152Gbps on LS side, Only Lane 0 on LS Side Active)
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1 AC Coupling
      2. 11.1.2 TLK10002 Clocks: REFCLK, CLKOUT - General Information
      3. 11.1.3 External Clock Connections
      4. 11.1.4 TLK10002 Control Pins and Interfaces
        1. 11.1.4.1 MDIO Interface
        2. 11.1.4.2 JTAG Interface
        3. 11.1.4.3 Unused Pins
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Receiving Notification of Documentation Updates
    2. 12.2 Community Resources
    3. 12.3 Trademarks
    4. 12.4 Electrostatic Discharge Caution
    5. 12.5 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6 Pin Configuration and Functions

CTR Package
144-Pin FCBGA
TLK10002 po_llse75.gif

Pin Functions

PIN DIRECTION
TYPE
SUPPLY		 DESCRIPTION
SIGNAL NO.
CHANNEL A
HSTXAP
HSTXAN		 D12
E12		 Output
CML
VDDA_HS		 Serial Transmit Channel A Output. HSTXAP and HSTXAN comprise the high speed side transmit direction Channel A differential serial output signal. During device reset (RESET_N asserted low) these pins are driven differential zero. These CML outputs must be AC-coupled.
HSRXAP
HSRXAN		 B12
A12		 Input
CML
VDDA_HS		 Serial Receive Channel A Input. HSRXAP and HSRXAN comprise the high speed side receive direction Channel A differential serial input signal. These CML input signals must be AC-coupled.
INA[3:0]P/N D1/E1
B2/C2
A1/B1
A4/A3		 Input
CML
VDDA_LS		 Parallel Channel A Inputs. INAP and INAN comprise the low speed side transmit direction Channel A differential input signals. Only INA[0] is used in the 1:1 mode, and only INA[1:0] are used in the 2:1 mode. These signals must be AC-coupled.
OUTA[3:0]P/N F3/E3
C4/C5
B5/B6
A6/A7		 Output
CML
VDDA_LS		 Parallel Channel A Outputs. OUTAP and OUTAN comprise the low speed side receive direction Channel A differential output signals. During device reset (RESET_N asserted low) these pins are driven differential zero. Only OUTA[0] is used in the 1:1 mode, and only OUTA[1:0] are used in the 2:1 mode. These signals must be AC-coupled.
LOSA E9 Output
LVCMOS
1.5V/1.8V
VDDO0
40Ω Driver		 Channel A Receive Loss Of Signal (LOS) Indicator.
LOSA=0: Signal detected.
LOSA=1: Loss of signal.
Loss of signal detection is based on the input signal level.
When HSRXAP/N has a differential input signal swing of <75 mVpp, LOSA will be asserted (if enabled). Once asserted, the input signal has to be > 150 mVpp for this LOS to be deasserted.
Other functions can be observed on LOSA in real-time, configured through MDIO.
During device reset (RESET_N asserted low) this pin is driven low. During pin-based power down (PDTRXA_N asserted low), this pin is floating. During register-based power down (1.15 asserted high), this pin is floating. NOTE: TI highly recommends that LOSA be brought to an easily accessible point on the application board (header), in the event that debug is required.
REFCLKA_SEL M9 Input
LVCMOS
1.5V/1.8V
VDDO0		 Reference Clock Select Channel A. This input, when low, selects REFCLK0P/N as the clock reference to Channel A SERDES. When high, REFCLK1P/N is selected as the clock reference to Channel A SERDES. If software control is desired (register bit 1.1), this input signal should be tied low. See Figure 13 for more detail. Default reference clock for Channel A is REFCLK0P/N.
CLKOUTAP/N C9/C10 Output
CML
DVDD		 Channel A High Speed Side Output Clock. By default, this output is enabled and outputs the high speed side Channel A recovered byte clock (high speed line rate divided by 20). Optionally it can be configured to output the VCO clock divided by 2. Additional MDIO-selectable divide ratios of 1, 2, 4, 5, 8, 10, 16, 20, and 25 are available. See Figure 13.
This CML output must be AC-coupled.
During device reset (RESET_N asserted low) these pins are driven differential zero.
During pin-based power down (PDTRXA_N and PDTRXB_N asserted low), these pins are floating.
During register-based power down (1.15 asserted high both channels), these pins are floating.
Channel A high speed side recovered byte clock can also be directed to CLKOUTBP/N pins through the MDIO interface.
LS_OK_IN_A B10 Input
LVCMOS
1.5V/1.8V
VDDO0		 Channel A Receive Lane Alignment Status Indicator.
Lane alignment status signal received from a Lane Alignment Slave on the link partner device.
LS_OK_IN_A=0: Channel A Link Partner Receive lanes not aligned.
LS_OK_IN_A=1: Channel A Link Partner Receive lanes aligned
LS_OK_OUT_A D9 Output
LVCMOS
1.5V/1.8V
VDDO0
40Ω Driver		 Channel A Transmit Lane Alignment Status Indicator.
Lane alignment status signal sent to a Lane Alignment Master on the link partner device.
LS_OK_OUT_A=0: Channel A Transmit lanes not aligned.
LS_OK_OUT_A=1: Channel A Transmit lanes aligned.
PDTRXA_N A8 Input
LVCMOS
1.5V/1.8V
VDDO0		 Transceiver Power Down. When this pin is held low (asserted), Channel A is placed in power down mode. When deasserted, Channel A operates normally. After deassertion, a software data path reset must be issued through the MDIO interface.
CHANNEL B
HSTXBP
HSTXBN		 K12
L12		 Output
CML
VDDA_HS		 Serial Transmit Channel B Output. HSTXBP and HSTXBN comprise the high speed side transmit direction Channel B differential serial output signal. During device reset (RESET_N asserted low) these pins are driven differential zero. These CML outputs must be AC-coupled.
HSRXBP
HSRXBN		 H12
G12		 Input
CML
VDDA_HS		 Serial Receive Channel B Input. HSRXBP and HSRXBN comprise the high-speed side receive direction Channel B differential serial input signal. These CML input signals must be AC-coupled.
INB[3:0]P/N M3/M4
L1/M1
K2/L2
H1/J1		 Input
CML
VDDA_LS		 Parallel Channel B Inputs. INBP and INBN comprise the low speed side transmit direction Channel B differential input signals. Only INB[0] is used in the 1:1 mode, and only INB[1:0] are used in the 2:1 mode. These signals must be AC-coupled.
OUTB[3:0]P/N M7/M6
L6/L5
K5/K4
J3/H3		 Output
CML
VDDA_LS		 Parallel Channel B Outputs. OUTBP and OUTBN comprise the low-speed side receive direction Channel B differential output signals. During device reset (RESET_N asserted low) these pins are driven differential zero. Only OUTB[0] is used in the 1:1 mode, and only OUTB[1:0] are used in the 2:1 mode. These signals must be AC-coupled.
LOSB K8 Output
LVCMOS
1.5V/1.8V
VDDO1
40Ω Driver		 Channel B Receive Loss Of Signal (LOS) Indicator.
LOSB=0: Signal detected.
LOSB=1: Loss of signal. Loss of signal detection is based on the input signal level. When HSRXBP/N has a differential input signal swing of <75 mVpp, LOSB will be asserted (if enabled). Once asserted, the input signal has to be > 150 mVpp for this LOS to be deasserted
Other functions can be observed on LOSB in real-time, configured through MDIO.
During device reset (RESET_N asserted low) this pin is driven low. During pin-based power down (PDTRXB_N asserted low), this pin is floating. During register-based power down (1.15 asserted high), this pin is floating.
TI highly recommends that LOSB be brought to an easily accessible point on the application board (header), in the event that debug is required.
REFCLKB_SEL H10 Input
LVCMOS
1.5V/1.8V
VDDO1		 Reference Clock Select Channel B. This input, when low, selects REFCLK0P/N as the clock reference to Channel B SERDES. When high, REFCLK1P/N is selected as the clock reference to Channel B SERDES. If software control is desired (register bit 1.1), this input signal should be tied low. See Figure 13 for more detail. Default reference clock for Channel B is REFCLK0P/N.
CLKOUTBP/N A9/A10 Output
CML
DVDD		 Channel B High Speed Side Output Clock. By default, this output is enabled and outputs the high-speed side Channel B recovered byte clock (high speed line rate divided by 20). Optionally it can be configured to output the VCO clock divided by 2. Additional MDIO-selectable divide ratios of 1, 2, 4, 5, 8, 10, 16, 20, and 25 are available. See Figure 13.
This CML output must be AC-coupled.
During device reset (RESET_N asserted low) these pins are driven differential zero. During pin-based power down (PDTRXA_N and PDTRXB_N asserted low), these pins are floating. During register-based power down (1.15 asserted high both channels), these pins are floating.
Channel B high-speed side recovered byte clock can also be directed to CLKOUTAP/N pins through the MDIO interface.
LS_OK_IN_B L8 Input
LVCMOS
1.5V/1.8V
VDDO1		 Channel B Receive Lane Alignment Status Indicator. Lane alignment status signal received from a Lane Alignment Slave on the link partner device.
LS_OK_IN_B=0: Channel B Link Partner Receive lanes not aligned.
LS_OK_IN_B=1: Channel B Link Partner Receive lanes aligned
LS_OK_OUT_B H9 Output
LVCMOS
1.5V/1.8V
VDDO1
40Ω Driver		 Channel B Transmit Lane Alignment Status Indicator. Lane alignment status signal sent to a Lane Alignment Master on the link partner device.
LS_OK_OUT_B=0: Channel B Transmit lanes not aligned.
LS_OK_OUT_B=1: Channel B Transmit lanes aligned.
PDTRXB_N J4 Input
LVCMOS
1.5V/1.8V
VDDO1		 Transceiver Power Down. When this pin is held low (asserted), Channel B is placed in power-down mode. When deasserted, Channel B operates normally. After deassertion, a software data path reset must be issued through the MDIO interface.
REFERENCE CLOCKS AND CONTROL AND MONITORING SIGNALS
REFCLK0P/N M10/M11 Input
LVDS/
LVPECL
DVDD		 Reference Clock Input Zero. This differential input is a clock signal used as a reference to one or both channels. The reference clock selection is done through MDIO or REFCLKA_SEL and REFCLKB_SEL pins. This input signal must be AC-coupled. If unused, REFCLK0P/N must be pulled down to GND through a shared 100-Ω resistor.
REFCLK1P/N K9/K10 Input
LVDS/
LVPECL
DVDD		 Reference Clock Input One. This differential input is a clock signal used as a reference to one or both channels. The reference clock selection is done through MDIO. This input signal must be AC-coupled. If unused, REFCLK1P/N must be pulled down to GND through a shared 100-Ω resistor.
PRBSEN B9 Input
LVCMOS
1.5V/1.8V
VDDO0		 Enable PRBS: When this pin is asserted high, the internal PRBS generator and verifier circuits are enabled on both transmit and receive data paths on high-speed and low-speed sides of both channels. This signal is logically OR’d with MDIO register bits B.7:6, and B.13:12. PRBS 231-1 is selected by default, and can be changed through MDIO.
PRBS_PASS J9 Output
LVCMOS
1.5V/1.8V
VDDO1
40Ω Driver		 Receive PRBS Error Free (Pass) Indicator.
When PRBS test is enabled (PRBSEN=1): PRBS_PASS=1 indicates that PRBS pattern reception is error free. PRBS_PASS=0 indicates that a PRBS error is detected. The channel, high-speed or low-speed side, and lane (for low-speed side) that this signal refers to is chosen through MDIO register bits 0.3:0.
During device reset (RESET_N asserted low) this pin is driven low.
During pin-based power down (PDTRXA_N and PDTRXB_N asserted low), this pin is floating.
During register-based power down, this pin is floating.
TI highly recommends that PRBS_PASS be brought to easily accessible point on the application board (header), in the event that debug is required.
PRTAD[4:0] M8
J6
L9
G9
E10		 Input
LVCMOS
1.5V/1.8V
VDDO[1:0]		 MDIO Port Address. Used to select the MDIO port address.
PRTAD[4:1] selects the MDIO port address. The TLK10002 has two different MDIO port addresses. Selecting a unique PRTAD[4:1] per TLK10002 device allows 16 TLK10002 devices per MDIO bus. Each channel can be accessed by setting the appropriate port address field within the serial interface protocol transaction.
The TLK10002 will respond if the 4 MSB’s of the port address field on MDIO protocol (PA[4:1]) matches PRTAD[4:1]. The LSB of port address field (PA[0]) determines which TLK10002 channel responds. Channel A responds when PA[0]=0 and Channel B responds when PA[0]=1.
PRTAD[0] is not used functionally, but is present for device testability and compatibility with other devices in the family of products. PRTAD[0] must be grounded on the application board.
RESET_N H5 Input
LVCMOS
1.5V/1.8V
VDDO1		 Low True Device Reset. RESET_N must be held asserted (low logic level) for at least 10 µs after device power stabilization.
MDC J8 Input
LVCMOS
with Hysteresis
1.5V/1.8V
VDDO1		 MDIO Clock Input. Clock input for the Clause 22 MDIO interface.
Note that an external pullup is generally not required on MDC.
MDIO J7 Input/Output
LVCMOS
1.5V/1.8V
VDDO1
25Ω Driver		 MDIO Data I/O. MDIO interface data input/output signal for the Clause 22 MDIO interface. This signal must be externally pulled up to VDDO, using a 2-kΩ resistor.
During device reset (RESET_N asserted low) this pin is floating. During register-based power down the management interface remains active for control register writes and reads. Certain status bits are not deterministic as their generating clock source may be disabled as a result of asserting either power down input signal. During pin-based power down (PDTRXA_N and PDTRXB_N asserted low), this pin is floating. During register-based power down (1.15 asserted high both channels), this pin is driven normally.
TDI C8 Input
LVCMOS
1.5V/1.8V
VDDO0
(Internal Pullup)		 JTAG Input Data. TDI is used to serially shift test data and test instructions into the device during the operation of the test port. In system applications where JTAG is not implemented, this input signal may be left floating.
During pin based power down (PDTRXA_N and PDTRXB_N asserted low), this pin is not pulled up. During register based power down (1.15 asserted high both channels), this pin is pulled up.
TDO D6 Output
LVCMOS
1.5V/1.8V
VDDO0
50Ω Driver		 JTAG Output Data. TDO is used to serially shift test data and test instructions out of the device during operation of the test port. When the JTAG port is not in use, TDO is in a high impedance state.
During device reset (RESET_N asserted low) this pin is floating.
During pin-based power down (PDTRXA_N and PDTRXB_N asserted low), this pin is floating.
During register-based power down (1.15 asserted high both channels), this pin is floating.
TMS B8 Input
LVCMOS
1.5V/1.8V
VDDO0
(Internal Pullup)		 JTAG Mode Select. TMS is used to control the state of the internal test-port controller. In system applications where JTAG is not implemented, this input signal can be left unconnected.
During pin based power down (PDTRXA_N and PDTRXB_N asserted low), this pin is not pulled up.
During register-based power down (1.15 asserted high both channels), this pin is pulled up.
TCK D8 Input
LVCMOS with Hysteresis
1.5V/1.8V
VDDO0		 JTAG Clock. TCK is used to clock state information and test data into and out of the device during boundary scan operation. In system applications where JTAG is not implemented, this input signal must be grounded.
TRST_N E5 Input
LVCMOS
1.5V/1.8V
VDDO0
(Internal Pulldown)		 JTAG Test Reset. TRST_N is used to reset the JTAG logic into system operational mode. This input can be left unconnected in the application and is pulled down internally, disabling the JTAG circuitry. If JTAG is implemented on the application board, this signal must be deasserted (high) during JTAG system testing, and otherwise asserted (low) during normal operation mode.
During pin-based power down (PDTRXA_N and PDTRXB_N asserted low), this pin is not pulled down. During register-based power down (1.15 asserted high both channels), this pin is pulled down.
TESTEN L10 Input
LVCMOS
1.5V/1.8V
VDDO1		 Test Enable. This signal is used during the device manufacturing process. It must be grounded through a resistor in the device application board. The application board must allow the flexibility of easily reworking this signal to a high level if device debug is necessary (by including an uninstalled resistor to VDDO).
GPI0 J10 Input
LVCMOS
1.5V/1.8V
VDDO1		 General Purpose Input Zero. This signal is used during the device manufacturing process. It must be grounded through a resistor on the device application board. The application board must also allow the flexibility of easily reworking this signal to a high level if device debug is necessary (by including an uninstalled resistor to VDDO).
AMUXA C11 Analog I/O SERDES Channel A Analog Testability I/O. This signal is used during the device manufacturing process. It must be left unconnected in the device application.
AMUXB D4 Analog I/O SERDES Channel B Analog Testability I/O. This signal is used during the device manufacturing process. It must be left unconnected in the device application.

Pin Functions – Power Pins(1)

PIN Type DESCRIPTION
SIGNAL BGA
VDDA_LS/HS D2, F2, G2,
J2 / F11, G10		 Power SERDES Analog Power. VDDA_LS and VDDA_HS provide supply voltage for the analog circuits on the low-speed and high-speed sides respectively. 1 V nominal. Can be tied together on the application board.
VDDT_LS/HS F4, G4 / F9 Power SERDES Analog Power. VDDT_LS and VDDT_HS provide termination and supply voltage for the analog circuits on the low-speed and high-speed sides respectively. 1 V nominal. Can be tied together on the application board.
VDDD E6, E8, F6, H6, H8 Power SERDES Digital Power. VDDD provides supply voltage for the digital circuits internal to the SERDES. 1 V nominal.
DVDD E7, F7, G6, G8, H7 Power Digital Core Power. DVDD provides supply voltage to the digital core. 1 V nominal.
VDDRA_LS/HS C3/E11 Power SERDES Analog Regulator Power. VDDRA_LS and VDDRA_HS provide supply voltage for the internal PLL regulator for Channel A low-speed and high-speed sides respectively. 1.5 V or 1.8 V nominal.
VDDRB_LS/HS K3/J11 Power SERDES Analog Regulator Power. VDDRB_LS and VDDRB_HS provide supply voltage for the internal PLL regulator for Channel B low-speed and high-speed sides respectively. 1.5 V or 1.8 V nominal.
VDDO[1:0] K7/C7 Power LVCMOS I/O Power. VDDO0 and VDDO1 provide supply voltage for the LVCMOS inputs and outputs. 1.5 V or 1.8 V nominal. Can be tied together on the application board.
VPP D7 Power Factory Program Voltage. Used during device manufacturing. The application must connect this power supply directly to DVDD.
VSS A2, A5, A11, B3, B4, B7, B11, C1, C6, C12, D3, D5, D10, D11, E2, E4, F1, F5, F8, F10, F12, G1, G3, G5, G7, G11, H2, H4, H11, J5, J12, K1, K6, K11, L3, L4, L7, L11, M2, M5, M12 Ground Ground. Common analog and digital ground.
(1) External AC-coupling is not needed if already included in the SFP+ module