SLLSEL3 Data sheet

SLLSEL3C July 2015 – September 2017 TLK10031

PRODUCTION DATA.

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Mechanical Data (Package|Pins)

CTR|144
- MPBGA06A

Thermal pad, mechanical data (Package|Pins)

Orderable Information

8 Applications and Implementation

NOTE

Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.

8.1 Application Information

The TLK10031 device can be used to convert between XAUI (on the low speed port) and 10GBASE-R signaling (on the high speed port). The high speed side of the device meets the requirements of the 10GBASE-KR physical layer standard for 10 Gbps data transmission over a PCB backplane. The device can also be used for optical physical layers (like 10GBASE-SR or 10GBASE-LR) by interfacing to optical modules requiring SFI or XFI electrical signaling. For optical use cases, KR-specific features like Clause 73 auto-negotiation and link training should be disabled.

8.2 Typical Application

A typical application for TLK10031 is to support 10 Gbps Ethernet data transmission over a backplane, e.g., between a network processor or MAC and switch ASIC located on separate cards within a router chassis. A block diagram of this application is shown in Figure 8-1.

TLK10031 application_circuit_sllsel3.gif

Figure 8-1 Typical Application Circuit

8.2.1 Design Requirements

For this design example, use the parameters shown in Table 8-1.

Table 8-1 Design Parameters

PARAMETER	VALUE
10GBASE-KR Interface Requirements
Signaling rate	10.3125 Gbps ±100 ppm
Differential peak-to-peak output voltage (maximum)	1200 mV
Total jitter (maximum)	0.28 UI
Encoding	64b/66b
Scrambling?	Yes
Auto-negotation?	Yes
Link training	Yes
XAUI Interface Requirements
Signaling rate per lane	3.125 Gbps ±100 ppm
Differential peak-to-peak output voltage (maximum)	1600 mV
Total jitter (maximum)	0.35 UI

8.2.2 Detailed Design Procedure

The TLK10031 should be powered via a 1-V (nominal) supply on the VDDD, VDDA, DVDD, VDDT, and VPP rails and by a 1.5-V or 1.8-V (nominal) supply on the VDDR and VDDO rails. The power supply accuracy should be 5% or better, and the user should be careful that resistive losses across the application PCB’s power distribution network do not cause the voltage present at the TLK10031 BGA balls to be below specification. If a switched-mode power supply is used, care should be taken to ensure low supply ripple

A differential reference clock must be provided to either the REFCLK0P/N or REFCLK1P/N input port. The clock signal should be AC-coupled and have a differential amplitude between 250 mV and 2000 mV peak-to-peak. For 10GBASE-R applications, the clock frequency should be either 156.25 MHz or 312.5 MHz and have an accuracy of 100 ppm. Because jitter on the reference clock can transfer through the TLK10031 PLLs and onto the serial outputs, it is best to keep the reference clock’s jitter as low as possible (that is, under 1 ps from 10 kHz to 20 MHz) in order to meet the requirements of IEEE 802.3.

All serial inputs and outputs should be laid out on the PCB following best practices for high speed signal integrity. Detailed layout recommendations are given in the Section 10 section.

8.2.3 Application Curves

The output eye diagram of the TLK10031 (operated at 10.3125 Gbps under nominal conditions) is shown Figure 8-2.

Figure 8-2 Eye Diagram of the TLK10031