SLLSEL3C July   2015  – September 2017 TLK10031

PRODUCTION DATA.  

  1. 1 Device Overview
    1. 1.1 Features
    2. 1.2 Applications
    3. 1.3 Description
  2. 2 Revision History
  3. 3 Description
  4. 4 Terminal Configuration and Functions
    1. 4.1 Pin Attributes
  5. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Thermal Information
    5. 5.5  Electrical Characteristics: High Speed Side Serial Transmitter
    6. 5.6  Electrical Characteristics: High Speed Side Serial Receiver
    7. 5.7  Electrical Characteristics: Low Speed Side Serial Transmitter
    8. 5.8  Electrical Characteristics: Low Speed Side Serial Receiver
    9. 5.9  Electrical Characteristics: LVCMOS (VDDO):
    10. 5.10 Electrical Characteristics: Clocks
    11. 5.11 Timing Requirements
    12. 5.12 Typical Characteristics
  6. 6 Parametric Measurement Information
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagrams
    3. 7.3 Feature Description
      1. 7.3.1  10GBASE-KR Transmit Data Path Overview
      2. 7.3.2  10GBASE-KR Receive Data Path Overview
      3. 7.3.3  Channel Synchronization Block
      4. 7.3.4  8B/10B Encoder
      5. 7.3.5  8B/10B Decoder
      6. 7.3.6  64B/66B Encoder/Scrambler
      7. 7.3.7  Forward Error Correction
      8. 7.3.8  64B/66B Decoder/Descrambler
      9. 7.3.9  Transmit Gearbox
      10. 7.3.10 Receive Gearbox
      11. 7.3.11 XAUI Lane Alignment / Code Gen (XAUI PCS)
      12. 7.3.12 Inter-Packet Gap (IPG) Characters
      13. 7.3.13 Clock Tolerance Compensation (CTC)
      14. 7.3.14 10GBASE-KR Auto-Negotiation
      15. 7.3.15 10GBASE-KR Link Training
      16. 7.3.16 10GBASE-KR Line Rate, PLL Settings, and Reference Clock Selection
      17. 7.3.17 10GBASE-KR Test Pattern Support
      18. 7.3.18 10GBASE-KR Latency
    4. 7.4 Device Functional Modes
      1. 7.4.1  10GBASE-KR Mode
      2. 7.4.2  1GBASE-KX Mode
        1. 7.4.2.1 Channel Sync Block
        2. 7.4.2.2 8b/10b Encoder and Decoder Blocks
        3. 7.4.2.3 TX CTC
        4. 7.4.2.4 1GBASE-KX Line Rate, PLL Settings, and Reference Clock Selection
        5. 7.4.2.5 1GBASE-KX Mode Latency
          1. 7.4.2.5.1 Test Pattern Generator
          2. 7.4.2.5.2 Test Pattern Verifier
      3. 7.4.3  General Purpose (10G) Serdes Mode Functional Description
        1. 7.4.3.1 General Purpose SERDES Transmit Data Path
      4. 7.4.4  General Purpose SERDES Receive Data Path
      5. 7.4.5  Channel Synchronization
      6. 7.4.6  8B/10B Encoder and Decoder
      7. 7.4.7  Lane Alignment Scheme for 8b/10b General Purpose Serdes Mode
      8. 7.4.8  Lane Alignment Components
      9. 7.4.9  Lane Alignment Operation
      10. 7.4.10 Line Rate, SERDES PLL Settings, and Reference Clock Selection for the General Purpose SERDES Mode
      11. 7.4.11 General Purpose SERDES Mode Test Pattern Support
      12. 7.4.12 General Purpose SERDES Mode Latency
        1. 7.4.12.1 Clocking Architecture (All Modes)
        2. 7.4.12.2 Integrated Smart Switch
      13. 7.4.13 Intelligent Switching Modes
      14. 7.4.14 Serial Loopback Modes
      15. 7.4.15 Latency Measurement Function (General Purpose SerDes Mode)
      16. 7.4.16 Power Down Mode
        1. 7.4.16.1 High Speed CML Output
        2. 7.4.16.2 High Speed Receiver
        3. 7.4.16.3 Loss of Signal Output Generation (LOS)
      17. 7.4.17 MDIO Management Interface
      18. 7.4.18 MDIO Protocol Timing
      19. 7.4.19 Clause 22 Indirect Addressing
      20. 7.4.20 Provisionable XAUI Clock Tolerance Compensation
        1. 7.4.20.1 Insertion:
        2. 7.4.20.2 Removal:
    5. 7.5 Register Maps
      1. 7.5.1 Register Bit Definitions
        1. 7.5.1.1 RW: Read-Write
        2. 7.5.1.2 RW/SC: Read-Write Self-Clearing
        3. 7.5.1.3 RO: Read-Only
        4. 7.5.1.4 RO/LH: Read-Only Latched High
        5. 7.5.1.5 RO/LL: Read-Only Latched Low
        6. 7.5.1.6 COR: Clear-On-Read
      2. 7.5.2 Vendor Specific Device Registers
        1. 7.5.2.1  GLOBAL_CONTROL_1 (register: 0x0000) (default: 0x0610) (device address: 0x1E)
        2. 7.5.2.2  CHANNEL_CONTROL_1 (register: 0x0001) (default: 0x0B00) (device address: 0x1E)
        3. 7.5.2.3  HS_SERDES_CONTROL_1 (register: 0x0002 ) (default: 0x831D) (device address: 0x1E)
        4. 7.5.2.4  HS_SERDES_CONTROL_2 (register: 0x0003) (default: 0xA848) (device address: 0x1E)
        5. 7.5.2.5  HS_SERDES_CONTROL_3 (register: 0x0004) (default: 0x1500) (device address: 0x1E)
        6. 7.5.2.6  HS_SERDES_CONTROL_4 (register: 0x0005) (default: 0x2000) (device address: 0x1E)
        7. 7.5.2.7  LS_SERDES_CONTROL_1 (register: 0x0006) (default: 0xF115) (device address: 0x1E)
        8. 7.5.2.8  LS_SERDES_CONTROL_2 (register: 0x0007) (default: 0xDC04) (device address: 0x1E)
        9. 7.5.2.9  LS_SERDES_CONTROL_3 (register: 0x0008) (default: 0x000D) (device address: 0x1E)
        10. 7.5.2.10 HS_OVERLAY_CONTROL (register: 0x0009) (default: 0x0380) (device address: 0x1E)
        11. 7.5.2.11 LS_OVERLAY_CONTROL (register: 0x000A) (default: 0x4000) (device address: 0x1E)
        12. 7.5.2.12 LOOPBACK_TP_CONTROL (register: 0x000B) (default: 0x0D10) (device address: 0x1E)
        13. 7.5.2.13 LS_CONFIG_CONTROL (register: 0x000C) (default: 0x0330) (device address: 0x1E)
        14. 7.5.2.14 LS_CONFIG_CONTROL (register: 0x000C) (default: 0x0330) (device address: 0x1E)
        15. 7.5.2.15 CLK_CONTROL (register: 0x000D) (default: 0x2F80) (device address: 0x1E)
        16. 7.5.2.16 RESET_CONTROL (register: 0x000E) (default: 0x0000) (device address: 0x1E)
        17. 7.5.2.17 CHANNEL_STATUS_1 (register: 0x000F) (default: 0x0000) (device address: 0x1E)
        18. 7.5.2.18 HS_ERROR_COUNTER (register: 0x0010) (default: 0x0FFFD) (device address: 0x1E)
        19. 7.5.2.19 LS_LN0_ERROR_COUNTER (register: 0x0011) (default: 0xFFFD) (device address: 0x1E)
        20. 7.5.2.20 LS_LN1_ERROR_COUNTER (register: 0x0012 ) (default: 0xFFFD) (device address: 0x1E)
        21. 7.5.2.21 LS_LN2_ERROR_COUNTER (register: 0x0013) (default: 0xFFFD) (device address: 0x1E)
        22. 7.5.2.22 LS_LN3_ERROR_COUNTER (register: 0x0014) (default: 0xFFFD) (device address: 0x1E)
        23. 7.5.2.23 LS_STATUS_1 (register: 0x0015) (default: 0x0000) (device address: 0x1E)
        24. 7.5.2.24 HS_STATUS_1 (register: 0x0016) (default: 0x0000) (device address: 0x1E)
        25. 7.5.2.25 DST_CONTROL_1 (register = 0x0017) (default = 0x2000) (device address: 0x1E)
        26. 7.5.2.26 DST_CONTROL_2 (register = 0x0018 ) (default = 0x0C20) (device address: 0x1E)
        27. 7.5.2.27 DSR_CONTROL_1 (register = 0x0019) (default = 0x2500) (device address: 0x1E)
        28. 7.5.2.28 DSR_CONTROL_2 (register = 0x001A) (default = 0x4C20) (device address: 0x1E)
        29. 7.5.2.29 DATA_SWITCH_STATUS (register = 0x001B) (default = 0x1020) (device address: 0x1E)
        30. 7.5.2.30 LS_CH_CONTROL_1 (register =0x001C) (default =0x0000) (device address: 0x1E)
        31. 7.5.2.31 HS_CH_CONTROL_1 (register = 0x001D) (default = 0x0000) (device address: 0x1E)
        32. 7.5.2.32 EXT_ADDRESS_CONTROL (register = 0x001E) (default = 0x0000) (device address: 0x1E)
        33. 7.5.2.33 EXT_ADDRESS_DATA (register = 0x001F) (default = 0x0000) (device address: 0x1E)
        34. 7.5.2.34 VS_10G_LN_ALIGN_ACODE_P (register =0x8003) (default = 0x0283) (device address: 0x1E)
        35. 7.5.2.35 VS_10G_LN_ALIGN_ACODE_N (register =0x8004 ) (default = 0x017C) (device address: 0x1E)
        36. 7.5.2.36 MC_AUTO_CONTROL (register = 0x8021) (default = 0x000F) (device address: 0x1E)
        37. 7.5.2.37 DST_ON_CHAR_CONTROL (register = 0x802A) (default = 0x02FD) (device address: 0x1E)
        38. 7.5.2.38 DST_OFF_CHAR_CONTROL (register = 0x802B ) (default = 0x02FD) (device address: 0x1E)
        39. 7.5.2.39 DST_STUFF_CHAR_CONTROL (register = 0x802C) (default = 0x0207) (device address: 0x1E)
        40. 7.5.2.40 DSR_ON_CHAR_CONTROL (register = 0x802D) (default = 0x02FD) (device address: 0x1E)
        41. 7.5.2.41 DSR_OFF_CHAR_CONTROL (register = 0X802E) (default = 0x02FD) (device address: 0x1E)
        42. 7.5.2.42 DSR_STUFF_CHAR_CONTROL (register = 0x802F) (default = 0x0207) (device address: 0x1E)
        43. 7.5.2.43 LATENCY_MEASURE_CONTROL (register = 0x8040) (default = 0x0000) (device address: 0x1E)
        44. 7.5.2.44 LATENCY_COUNTER_2 (register = 0x8041) (default =0x0000) (device address: 0x1E)
        45. 7.5.2.45 LATENCY_COUNTER_1 (register = 0x8042) (default = 0x0000) (device address: 0x1E)
        46. 7.5.2.46 TRIGGER_LOAD_CONTROL (register =0x8100) (default = 0x0000) (device address: 0x1E)
        47. 7.5.2.47 TRIGGER_EN_CONTROL (register = 0x8101) (default = 0x0000) (device address: 0x1E)
      3. 7.5.3 PMA/PMD Registers
        1. 7.5.3.1  PMA_CONTROL_1 (register = 0x0000) (default = 0x0000) (device address: 0x01)
        2. 7.5.3.2  PMA_STATUS_1 (register = 0x0001) (default = 0x0002) (device address: 0x01)
        3. 7.5.3.3  PMA_DEV_IDENTIFIER_1 (register = 0x0002) (default = 0x4000) (device address: 0x01)
        4. 7.5.3.4  PMA_DEV_IDENTIFIER_2 (register = 0x0003) (default = 0x5100) (device address: 0x01)
        5. 7.5.3.5  PMA_SPEED_ABILITY (register = 0x0004) (default = 0x0011) (device address: 0x01)
        6. 7.5.3.6  PMA_DEV_PACKAGE_1 (register = 0x0005) (default = 0x000B) (device address: 0x01)
        7. 7.5.3.7  PMA_DEV_PACKAGE_2 (register = 0x0006) (default = 0x4000) (device address: 0x01)
        8. 7.5.3.8  PMA_DEV_PACKAGE_2 (register = 0x0006) (default = 0x4000) (device address: 0x01)
        9. 7.5.3.9  PMA_RX_SIGNAL_DET_STATUS (register = 0x000A) (default = 0x0000) (device address: 0x01)
        10. 7.5.3.10 PMA_EXTENDED_ABILITY (register = 0x000B) (default = 0x0050) (device address: 0x01)
        11. 7.5.3.11 LT_TRAIN_CONTROL (register =0x0096) (default = 0x0002) (device address: 0x01)
        12. 7.5.3.12 LT_TRAIN_STATUS (register = 0x0097) (default = 0x0000) (device address: 0x01)
        13. 7.5.3.13 LT_LINK_PARTNER_CONTROL (register = 0x0098) (default = 0x0000) (device address: 0x01)
        14. 7.5.3.14 LT_LINK_PARTNER_STATUS (register = 0x0099) (default = 0x0000) (device address: 0x01)
        15. 7.5.3.15 LT_LOCAL_DEVICE_CONTROL (register = 0x009A) (default = 0x0000) (device address: 0x01)
        16. 7.5.3.16 LT_LOCAL_DEVICE_STATUS (register = 0x009B) (default = 0x0000) (device address: 0x01)
        17. 7.5.3.17 KX_STATUS (register = 0x00A1) (default = 0x3000) (device address: 0x01)
        18. 7.5.3.18 KR_FEC_ABILITY (register = 0x00AA) (default = 0x0003) (device address: 0x01)
        19. 7.5.3.19 KR_FEC_CONTROL (register = 0x00AB) (default = 0x0000) (device address: 0x01)
        20. 7.5.3.20 KR_FEC_C_COUNT_1 (register = 0x00AC) (default = 0x0000) (device address: 0x01)
        21. 7.5.3.21 KR_FEC_C_COUNT_2 (register = 0x00AD) (default = 0x0000) (device address: 0x01)
        22. 7.5.3.22 KR_FEC_UC_COUNT_1 (register = 0x00AE) (default = 0x0000) (device address: 0x01)
        23. 7.5.3.23 KR_FEC_UC_COUNT_2 (register = 0x00AF) (default = 0x0000) (device address: 0x01)
        24. 7.5.3.24 KR_VS_FIFO_CONTROL_1 (register = 0x8001) (default = 0xCC4C) (device address: 0x01)
        25. 7.5.3.25 KR_VS_TP_GEN_CONTROL (register =0x8002) (default = 0x0000) (device address: 0x01)
        26. 7.5.3.26 KR_VS_TP_VER_CONTROL (register = 0x8003) (default = 0x0000) (device address: 0x01)
        27. 7.5.3.27 KR_VS_CTC_ERR_CODE_LN0 (register = 0x8005) (default = 0xCE00) (device address: 0x01)
        28. 7.5.3.28 KR_VS_CTC_ERR_CODE_LN1 (register = 0x8006) (default =0x0000) (device address: 0x01)
        29. 7.5.3.29 KR_VS_CTC_ERR_CODE_LN2 (register = 0x8007) (default = 0x0000) (device address: 0x01)
        30. 7.5.3.30 KR_VS_CTC_ERR_CODE_LN3 (register = 0x8008) (default = 0x0080) (device address: 0x01)
        31. 7.5.3.31 KR_VS_LN0_EOP_ERROR_COUNTER (register = 0x8010) (default = 0xFFFD) (device address: 0x01)
        32. 7.5.3.32 KR_VS_LN1_EOP_ERROR_COUNTER (register = 0x8011) (default = 0xFFFD) (device address: 0x01)
        33. 7.5.3.33 KR_VS_LN2_EOP_ERROR_COUNTER (register = 0x8012) (default = 0xFFFD) (device address: 0x01)
        34. 7.5.3.34 KR_VS_LN3_EOP_ERROR_COUNTER (register =0x8013 ) (default = 0xFFFD) (device address: 0x01)
        35. 7.5.3.35 KR_VS_TX_CTC_DROP_COUNT (register = 0x8014) (default = 0xFFFD) (device address: 0x01)
        36. 7.5.3.36 KR_VS_TX_CTC_INSERT_COUNT (register = 0x8015) (default = 0xFFFD) (device address: 0x01)
        37. 7.5.3.37 KR_VS_RX_CTC_DROP_COUNT (register = 0x8016) (default = 0xFFFD) (device address: 0x01)
        38. 7.5.3.38 KR_VS_RX_CTC_INSERT_COUNT (register = 0x8017) (default = 0xFFFD) (device address: 0x01)
        39. 7.5.3.39 KR_VS_STATUS_1 (register = 0x8018) (default = 0x0000) (device address: 0x01)
        40. 7.5.3.40 KR_VS_TX_CRCJ_ERR_COUNT_1 (register = 0x8019) (default = 0xFFFF) (device address: 0x01)
        41. 7.5.3.41 KR_VS_TX_CRCJ_ERR_COUNT_2 (register = 0x801A) (default = 0xFFFD) (device address: 0x01)
        42. 7.5.3.42 KR_VS_TX_LN0_HLM_ERR_COUNT (register = 0x801B) (default = 0xFFFD) (device address: 0x01)
        43. 7.5.3.43 KR_VS_TX_LN1_HLM_ERR_COUNT (register = 0x801C) (default = 0xFFFD) (device address: 0x01)
        44. 7.5.3.44 KR_VS_TX_LN2_HLM_ERR_COUNT (register = 0x801D) (default = 0xFFFD) (device address: 0x01)
        45. 7.5.3.45 KR_VS_TX_LN3_HLM_ERR_COUNT (register = 0x801E) (default = 0xFFFD) (device address: 0x01)
        46. 7.5.3.46 LT_VS_CONTROL_2 (register = 0x9001) (default = 0x0000) (device address: 0x01)
      4. 7.5.4 PCS Registers
        1. 7.5.4.1  PCS_CONTROL (register = 0x0000) (default = 0x0000) (device address: 0x03)
        2. 7.5.4.2  PCS_STATUS_1 (register = 0x0001) (default = 0x0002) (device address: 0x03)
        3. 7.5.4.3  PCS_STATUS_2 (register = 0x0008) (default = 0x8001) (device address: 0x03)
        4. 7.5.4.4  KR_PCS_STATUS_1 (register = 0x0020) (default = 0x0004) (device address: 0x03)
        5. 7.5.4.5  KR_PCS_STATUS_2 (register = 0x0021) (default = 0x0000) (device address: 0x03)
        6. 7.5.4.6  PCS_TP_SEED_A0 (register = 0x0022) (default = 0x0000) (device address: 0x03)
        7. 7.5.4.7  PCS_TP_SEED_A1 (register = 0x0023) (default = 0x0000) (device address: 0x03)
        8. 7.5.4.8  PCS_TP_SEED_A2 (register = 0x0024) (default = 0x0000) (device address: 0x03)
        9. 7.5.4.9  PCS_TP_SEED_A3 (register = 0x0025) (default = 0x0000) (device address: 0x03)
        10. 7.5.4.10 PCS_TP_SEED_B0 (register = 0x0026) (default = 0x0000) (device address: 0x03)
        11. 7.5.4.11 PCS_TP_SEED_B1 (register = 0x0027) (default = 0x0000) (device address: 0x03)
        12. 7.5.4.12 PCS_TP_SEED_B2 (register = 0x0028) (default = 0x0000) (device address: 0x03)
        13. 7.5.4.13 PCS_TP_SEED_B3 (register = 0x0029) (default = 0x0000) (device address: 0x03)
        14. 7.5.4.14 PCS_TP_CONTROL (register = 0x002A) (default = 0x0000) (device address: 0x03)
        15. 7.5.4.15 PCS_TP_ERR_COUNT (register = 0x002B) (default = 0x0000) (device address: 0x03)
        16. 7.5.4.16 PCS_VS_CONTROL (register = 0x8000) (default = 0x00B0) (device address: 0x03)
        17. 7.5.4.17 PCS_VS_STATUS (register = 0x8010) (default = 0x00FD) (device address: 0x03)
      5. 7.5.5 Auto-Negotiation Registers
        1. 7.5.5.1  AN_CONTROL (register = 0x0000) (default = 0x3000) (device address: 0x07)
        2. 7.5.5.2  AN_STATUS (register = 0x0001) (default = 0x0088) (device address: 0x07)
        3. 7.5.5.3  AN_DEV_PACKAGE (register = 0x0005) (default = 0x0080) (device address: 0x07)
        4. 7.5.5.4  AN_ADVERTISEMENT_1 (register = 0x0010) (default = 0x1001) (device address: 0x07)
        5. 7.5.5.5  AN_ADVERTISEMENT_2 (register = 0x0011) (default = 0x0080) (device address: 0x07)
        6. 7.5.5.6  AN_ADVERTISEMENT_3 (register = 0x0012) (default = 0x4000) (device address: 0x07)
        7. 7.5.5.7  AN_LP_ADVERTISEMENT_1 (register = 0x0013) (default = 0x0001) (device address: 0x07)
        8. 7.5.5.8  AN_LP_ADVERTISEMENT_2 (register = 0x0014) (default = 0x0000) (device address: 0x07)
        9. 7.5.5.9  AN_LP_ADVERTISEMENT_3 (register = 0x0015) (default = 0x0000) (device address: 0x07)
        10. 7.5.5.10 AN_XNP_TRANSMIT_1 (register = 0x0016) (default = 0x2000) (device address: 0x07)
        11. 7.5.5.11 AN_XNP_TRANSMIT_2 (register = 0x0017) (default = 0x0000) (device address: 0x07)
        12. 7.5.5.12 AN_XNP_TRANSMIT_3 (register = 0x0018) (default = 0x0000) (device address: 0x07)
        13. 7.5.5.13 AN_LP_XNP_ABILITY_1 (register = 0x0019) (default = 0x0000) (device address: 0x07)
        14. 7.5.5.14 AN_LP_XNP_ABILITY_2 (register = 0x001A) (default = 0x0000) (device address: 0x07)
        15. 7.5.5.15 AN_LP_XNP_ABILITY_3 (register = 0x001B) (default = 0x0000) (device address: 0x07)
        16. 7.5.5.16 AN_BP_STATUS (register = 0x0030) (default = 0x0001) (device address: 0x07)
  8. 8 Applications and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 TLK10031 High-Speed Data Path
        1. 10.1.1.1 Layout Recommendations for High-Speed Signals
        2. 10.1.1.2 AC-coupling
      2. 10.1.2 TLK10031 Clocks: REFCLK, CLKOUT
        1. 10.1.2.1 General Information
        2. 10.1.2.2 External Clock Connections
        3. 10.1.2.3 TLK10031 Control Pins and Interfaces
          1. 10.1.2.3.1 MDIO Interface
          2. 10.1.2.3.2 JTAG Interface
          3. 10.1.2.3.3 Unused Pins
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Receiving Notification of Documentation Updates
    2. 11.2 Community Resources
    3. 11.3 Trademarks
    4. 11.4 Electrostatic Discharge Caution
    5. 11.5 Glossary
  12. 12Mechanical Packaging and Orderable Information
    1. 12.1 Packaging Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6 Parametric Measurement Information

TLK10031 tx_op_wf_llsec0.gif Figure 6-1 Transmit Output Waveform Parameter Definitions
TLK10031 cursor_swing_llsec0.gif Figure 6-2 Pre/Post Cursor Swing Definitions
TLK10031 rd_wrt_tim_llsec0.gif Figure 6-3 MDIO Read/Write Timing
TLK10031 JTAG_tim_llsec0.gif Figure 6-4 JTAG Timing