SLLSEL3 Data sheet

SLLSEL3C July 2015 – September 2017 TLK10031

PRODUCTION DATA.

Package Options

Mechanical Data (Package|Pins)

CTR|144
- MPBGA06A

Thermal pad, mechanical data (Package|Pins)

Orderable Information

4 Terminal Configuration and Functions

A 13-mm x 13-mm, 144-pin PBGA package with a ball pitch of 1 mm is used.

TLK10031 Pinout

4.1 Pin Attributes

Table 4-1 Pin Description - Signal Pins

PIN		I/O TYPE	DESCRIPTION
NAME	NO.	I/O TYPE	DESCRIPTION
HSTXAP HSTXAN	D12 E12	Output CML VDDA_HS	High Speed Transmit Output. HSTXAP and HSTXAN comprise the high speed side transmit direction differential serial output signal. During device reset (RESET_N asserted low) these pins are driven differential zero. These CML outputs must be AC coupled.
HSRXAP HSRXAN	B12 A12	Input CML VDDA_HS	High Speed Receive Input. HSRXAP and HSRXAN comprise the high speed side receive direction differential serial input signal. These CML input signals must be AC coupled.
INA[3:0]P/N	D1/E1 B2/C2 A1/B1 A4/A3	Input CML VDDA_LS	Low Speed Inputs. INAP and INAN comprise the low speed side transmit direction differential input signals. These signals must be AC coupled.
OUTA[3:0]P/N	F3/E3 C4/C5 B5/B6 A6/A7	Output CML VDDA_LS	Low Speed Outputs. OUTAP and OUTAN comprise the low speed side receive direction differential output signals. During device reset (RESET_N asserted low) these pins are driven differential zero. These signals must be AC coupled.
LOSA	E9	Output LVCMOS 1.5V/1.8V VDDO0 40Ω Driver	Receive Loss Of Signal (LOS) Indicator. LOS = 0: Signal detected. LOS = 1: Loss of signal. Loss of signal detection is based on the input signal level. When HSRXAP/N has a differential input signal swing of ≤75 mV_pp, LOSA is asserted (if enabled). If the input signal is greater than 150 mV_pp, LOSA is deasserted. Outside of these ranges, the LOS indication is undefined.
			Other functions can be observed on LOSA real-time, configured via MDIO
			During device reset (RESET_N asserted low) this pin is driven low. During pin based power down (PDTRXA_N asserted low), this pin is floating. During register based power down, this pin is floating.
			It is highly recommended that LOSA be brought to an easily accessible point on the application board (header) in the event that debug is required.
LS_OK_IN_A	B10	Input LVCMOS 1.5V/1.8V VDDO0	Receive Lane Alignment Status Indicator. Lane alignment status signal received from a Lane Alignment Slave on the link partner device. Valid in 10G General Purpose Serdes Mode. LS_OK_IN_A = 0: Link partner receive lanes not aligned. LS_OK_IN_A = 1: Link partner receive lanes aligned
LS_OK_OUT_A	D9	Output LVCMOS 1.5V/1.8V VDDO 40Ω Driver	Transmit Lane Alignment Status Indicator. Lane alignment status signal sent to a Lane Alignment Master on the link partner device. Valid in 10G General Purpose Serdes Mode. LS_OK_OUT_A = 0: Link partner transmit lanes not aligned. LS_OK_OUT_A = 1: Link partner transmit lanes aligned.
PDTRXA_N	A8	Input LVCMOS 1.5V/1.8V VDDO0	Transceiver Power Down. When this pin is held low (asserted), the channel is placed in power down mode. When deasserted, the channel operates normally. After deassertion, a software data path reset should be issued through the MDIO interface.
RESERVED PINS
RSV[7:0]	L12, K12, K8, H12, H9, G12, A10, A9		Reserved. It should be left unconnected in the device application.
REFERENCE CLOCKS, OUTPUT CLOCKS, AND CONTROL AND MONITORING SIGNALS
REFCLK0P/N	M10 M11	Input LVDS/ LVPECL DVDD	Reference Clock Input Zero. This differential input is a clock signal used as a reference to channel A. The reference clock selection is done through MDIO. This input signal must be AC coupled. If unused, REFCLK0P/N should be pulled down to GND through a shared 100 Ω resistor.
REFCLK1P/N	K9 K10	Input LVDS/ LVPECL DVDD	Reference Clock Input One. This differential input is a clock signal used as a reference to channel A. The reference clock selection is done through MDIO. This input signal must be AC coupled. If unused, REFCLK1P/N should be pulled down to GND through a shared 100 Ω resistor.
CLKOUTAP/N	C9 C10	Output CML DVDD	Channel Output Clock. By default, this outputs is enabled, and outputs the high speed side recovered byte clock (high speed line rate divided by 16 or 20). Optionally, they can be configured to output the VCO clock divided by 2. (Note: for full rates, VCO/2 pre-divided clocks will be equivalent to the line rate divided by 8; for sub-rates, VCO/2 pre-divided clocks will be equivalent to the line rate divided by 4).
			These CML outputs must be AC coupled.
			During device reset (RESET_N asserted low), pin-based power down (PDTRXA_N asserted low), or register-based power down, these pins are floating.
PRBSEN	B9	Input LVCMOS 1.5V/1.8V VDDO0	Enable PRBS: When this pin is asserted high, the internal PRBS generator and verifier circuits are enabled on both transmit and receive data paths on high speed and low speed sides.
PRBSEN	B9	Input LVCMOS 1.5V/1.8V VDDO0	The PRBS 2⁷-1 pattern is selected by default, and can be changed through MDIO.
PRBS_PASS	J9	Output LVCMOS 1.5V/1.8V VDDO1 40Ω Driver	Receive PRBS Error Free (Pass) Indicator. When PRBS test is enabled (PRBSEN=1): PRBS_PASS = 1 indicates that PRBS pattern reception is error free. PRBS_PASS = 0 indicates that a PRBS error is detected. The high speed or low speed side, and lane (for low speed side) that this signal refers to is chosen through MDIO.
			During device reset (RESET_N asserted low) this pin is driven high. During pin based power down (PDTRXA_N asserted low), this pin is floating. During register based power down, this pin is floating.
			It is highly recommended that PRBS_PASS be brought to easily accessible point on the application board (header), in the event that debug is required.
ST	M9	Input LVCMOS 1.5V/1.8V VDDO[1:0]	MDIO Select. Used to select Clause 22 (=1) or Clause 45 (=0) operation. Note that selecting clause 22 will impact mode availability. See MODE_SEL.
ST	M9	Input LVCMOS 1.5V/1.8V VDDO[1:0]	A hard or soft reset must be applied after a change of state occurs on this input signal.
MODE_SEL	H10	Input LVCMOS 1.5V/1.8V VDDO[1:0]	Device Operating Mode Select. Used together with ST pin to select device operating mode. See Table 7-2 for details.
PRTAD[4:0]	M8 J6 L9 G9 E10	Input LVCMOS 1.5V/1.8V VDDO[1:0]	MDIO Port Address. Used to select the MDIO port address.
			PRTAD[4:1] selects the MDIO port address. The TLK10031 has one MDIO port addresses. Selecting a unique PRTAD[4:1] per TLK10031 device allows 16 TLK10031 devices per MDIO bus.
			The TLK10031 responds if the 4 MSB’s of the port address field on MDIO protocol (PA[4:1]) matches PRTAD[4:1], and PA[0] = 0.
			PRTAD0 is not needed for port addressing, but can be used as a general purpose input pin to control the switching function or the stopwatch latency measurement. If these functions are not needed, PRTAD0 should be grounded on the application board.
RESET_N	H5	Input LVCMOS 1.5V/1.8V VDDO01	Low True Device Reset. RESET_N must be held asserted (low logic level) for at least 10 µs after device power stabilization.
MDC	J8	Input LVCMOS with Hysteresis 1.5V/1.8V VDDO1	MDIO Clock Input. Clock input for the MDIO interface. Note that an external pullup is generally not required on MDC except if driven by an open-drain/open-collector clock source.
MDIO	J7	Input/ Output LVCMOS 1.5V/1.8V VDDO1 25Ω Driver	MDIO Data I/O. MDIO interface data input/output signal for the MDIO interface. This signal must be externally pulled up to VDDO using a 2-kΩ resistor.
MDIO	J7	Input/ Output LVCMOS 1.5V/1.8V VDDO1 25Ω Driver	During device reset (RESET_N asserted low) this pin is floating. During software initiated power down the management interface remains active for control register writes and reads. Certain status bits will not be deterministic as their generating clock source may be disabled as a result of asserting either power down input signal. During pin based power down (PDTRXA_N asserted low), this pin is floating. During register based power down, this pin is driven normally.
TDI	C8	Input LVCMOS 1.5V/1.8V VDDO0 (Internal Pullup)	JTAG Input Data. TDI is used to serially shift test data and test instructions into the device during the operation of the test port. In system applications where JTAG is not implemented, this input signal may be left floating. During pin based power down (PDTRXA_N asserted low), this pin is not pulled up. During register based power down, this pin is pulled up normally.
TDO	D6	Output LVCMOS 1.5V/1.8V VDDO0 50Ω Driver	JTAG Output Data. TDO is used to serially shift test data and test instructions out of the device during operation of the test port. When the JTAG port is not in use, TDO is in a high impedance state. During device reset (RESET_N asserted low) this pin is floating. During pin based power down (PDTRXA_N asserted low), this pin is not pulled up. During register based power down, this pin is pulled up normally.
TMS	B8	Input LVCMOS 1.5V/1.8V VDDO0 (Internal Pullup)	JTAG Mode Select. TMS is used to control the state of the internal test-port controller. In system applications where JTAG is not implemented, this input signal can be left unconnected. During pin based power down (PDTRXA_N asserted low), this pin is not pulled up. During register based power down, this pin is pulled up normally.
TCK	D8	Input LVCMOS with Hysteresis 1.5V/1.8V VDDO0	JTAG Clock. TCK is used to clock state information and test data into and out of the device during boundary scan operation. In system applications where JTAG is not implemented, this input signal should be grounded.
TRST_N	E5	Input LVCMOS 1.5V/1.8V VDDO0 (Internal Pulldown)	JTAG Test Reset. TRST_N is used to reset the JTAG logic into system operational mode. This input can be left unconnected in the application and is pulled down internally, disabling the JTAG circuitry. If JTAG is implemented on the application board, this signal should be deasserted (high) during JTAG system testing, and otherwise asserted (low) during normal operation mode. During pin based power down (PDTRXA_N asserted low), this pin is not pulled up. During register based power down, this pin is pulled up normally.
TESTEN	L10	Input LVCMOS 1.5V/1.8V VDDO1	Test Enable. This signal is used during the device manufacturing process. It should be grounded through a resistor in the device application board. The application board should allow the flexibility of easily reworking this signal to a high level if device debug is necessary (by including an uninstalled resistor to VDDO).
GPI0	L8, J4, J10	Input LVCMOS 1.5V/1.8V VDDO1	General Purpose Input. his signal is used during the device manufacturing process. It should be grounded through a resistor on the device application board.
AMUX0	C11	Analog I/O	SERDES Analog Testability I/O. This signal is used during the device manufacturing process. It should be left unconnected in the device application.
AMUX1	D4	Analog I/O	SERDES Analog Testability I/O. This signal is used during the device manufacturing process. It should be left unconnected in the device application.

Table 4-2 Pin Description - Power Pins

PIN		I/O TYPE	DESCRIPTION
NAME	NO.	I/O TYPE	DESCRIPTION
VDDA_LS/HS	D2, F2, G2, J2, G10, F11	Input Power	SERDES Analog Power. VDDA_LS and VDDA_HS provide supply voltage for the analog circuits on the low-speed and high-speed sides respectively. 1.0V nominal. Can be tied together on the application board.
VDDT_LS/HS	F4, G4, F9	Input Power	SERDES Analog Power. VDDT_LS and VDDT_HS provide termination and supply voltage for the analog circuits on the low-speed and high-speed sides respectively. 1.0V nominal. Can be tied together on the application board.
VDDD	E6, F6, H6, E8, H8	Input Power	SERDES Digital Power. VDDD provides supply voltage for the digital circuits internal to the SERDES. 1 V nominal.
DVDD	G6, E7, F7, H7, G8	Input Power	Digital Core Power. DVDD provides supply voltage to the digital core. 1 V nominal.
VDDRA_LS/HS	C3, K3, J11 E11	Input Power	SERDES Analog Regulator Power. VDDRA_LS and VDDRA_HS provide supply voltage for the internal PLL regulator for low speed and high speed sides respectively. 1.5 V or 1.8 V nominal.
VDDO[1:0]	K7 C7	Input Power	LVCMOS I/O Power. VDDO0 and VDDO1 provide supply voltage for the LVCMOS inputs and outputs. 1.5 V or 1.8 V nominal. Can be tied together on the application board.
VPP	D7	Input Power	Factory Program Voltage. Used during device manufacturing. The application must connect this power supply directly to DVDD.
VSS	A2, A5, A11, B3, B4, B7, B11, C1, C6, C12, D3, D5, D10, D11, E2, E4, F1, F5, F8, F10, F12, G1, G3, G5, G7, G11, H1, H2, H4, H3, H11, J1, J3, J5, J12, K1, K2, K4, K5, K6, K11, L1, L2, L3, L4, L5, L6, L7, L11, M1, M2, M3, M4, M5, M6, M7, M12	Ground	Ground. Common analog and digital ground.