SLLSEC7A August 2012 – October 2015 TLK10034
PRODUCTION DATA.
A 19-mm x 19-mm, 324-pin PBGA package with a ball pitch of 1 mm is used. The device pin-out is as shown in Figure 3-1, Figure 3-2 and is described in detail in Table 3-1 and Table 3-2.
The details of the terminal functions of the TLK10034 are provided in Table 3-1 and Table 3-2.
PIN | DIRECTION TYPE SUPPLY |
DESCRIPTION | |
---|---|---|---|
SIGNAL | BGA | ||
CHANNEL A | |||
HSTXAP HSTXAN |
A8 A9 |
Output CML VDDA_HS |
High Speed Transmit Channel A Output. HSTXAP and HSTXAN comprise the high speed side transmit direction Channel A differential serial output signal. During device reset (RESET_N asserted low) these pins are driven differential zero. These CML outputs must be AC coupled. |
HSRXAP HSRXAN |
A6 A5 |
Input CML VDDA_HS |
High Speed Receive Channel A Input. HSRXAP and HSRXAN comprise the high speed side receive direction Channel A differential serial input signal. These CML input signals must be AC coupled. |
INA[3:0]P/N | G1/H1 D1/E1 B2/B1 A3/A2 |
Input CML VDDA_LS |
Low Speed Channel A Inputs. INAP and INAN comprise the low speed side transmit direction Channel A differential input signals. These signals must be AC coupled. |
OUTA[3:0]P/N | H4/J4 F3/G3 D4/E4 C3/D3 |
Output CML VDDA_LS |
Low Speed Channel A Outputs. OUTAP and OUTAN comprise the low speed side receive direction Channel A differential output signals. During device reset (RESET_N asserted low) these pins are driven differential zero. These signals must be AC coupled. |
LOSA | D6 | Output LVCMOS 1.5V/1.8V VDDO0 40Ω Driver |
Channel A Receive Loss Of Signal (LOS) Indicator.
LOSA=0: Signal detected. LOSA=1: Loss of signal. Loss of signal detection is based on the input signal level. When HSRXAP/N has a differential input signal swing of ≤65 mVpp, LOSA will be asserted (if enabled). If the input signal is greater than 175 mVp-p, LOS will be deasserted. Outside of these ranges, the LOS indication is undefined. |
Other functions can be observed on LOSA real-time, configured via MDIO | |||
During device reset (RESET_N asserted low) this pin is driven low. During pin based power down (PDTRXA_N asserted low), this pin is floating. During register based power down (30.1.15 asserted high), this pin is floating. | |||
It is highly recommended that LOSA be brought to an easily accessible point on the application board (header) in the event that debug is required. | |||
LS_OK_IN_A | F6 | Input LVCMOS 1.5V/1.8V VDDO0 |
Channel A Receive Lane Alignment Status Indicator.
Lane alignment status signal received from a Lane Alignment Slave on the link partner device. Valid in 10G General Purpose Serdes Mode. LS_OK_IN_A=0: Channel A link partner receive lanes not aligned. LS_OK_IN_A=1: Channel A link partner receive lanes aligned |
LS_OK_OUT_A | J6 | Output LVCMOS 1.5V/1.8V VDDO0 40Ω Driver |
Channel A Transmit Lane Alignment Status Indicator.
Lane alignment status signal sent to a Lane Alignment Master on the link partner device. Valid in 10G General Purpose Serdes Mode. LS_OK_OUT_A=0: Channel A link partner transmit lanes not aligned. LS_OK_OUT_A=1: Channel A link partner transmit lanes aligned. |
PDTRXA_N | E6 | Input LVCMOS 1.5V/1.8V VDDO0 |
Transceiver Power Down.
When this pin is held low (asserted), Channel A is placed in power down mode. When deasserted, Channel A operates normally. After deassertion, a software data path reset should be issued through the MDIO interface. |
CHANNEL B | |||
HSTXBP HSTXBN |
V5 V4 |
Output CML VDDA_HS |
High Speed Transmit Channel B Output. HSTXBP and HSTXBN comprise the high speed side transmit direction Channel B differential serial output signal. During device reset (RESET_N asserted low) these pins are driven differential zero. These CML outputs must be AC coupled. |
HSRXBP HSRXBN |
V7 V8 |
Input CML VDDA_HS |
High Speed Receive Channel B Input. HSRXBP and HSRXBN comprise the high speed side receive direction Channel B differential serial input signal. These CML input signals must be AC coupled. |
INB[3:0]P/N | U1/V1 T2/U2 P1/R1 L1/M1 |
Input CML VDDA_LS |
Low Speed Channel B Inputs. INBP and INBN comprise the low speed side transmit direction Channel B differential input signals. These signals must be AC coupled. |
OUTB[3:0]P/N | R3/P3 N4/M4 L3/K3 K2/J2 |
Output CML VDDA_LS |
Low Speed Channel B Outputs. OUTBP and OUTBN comprise the low speed side receive direction Channel B differential output signals. During device reset (RESET_N asserted low) these pins are driven differential zero. These signals must be AC coupled. |
LOSB | P7 | Output LVCMOS 1.5V/1.8V VDDO3 40Ω Driver |
Channel B Receive Loss Of Signal (LOS) Indicator.
LOSB=0: Signal detected. LOSB=1: Loss of signal. Loss of signal detection is based on the input signal level. When HSRXBP/N has a differential input signal swing of ≤65 mVpp, LOSB will be asserted (if enabled). If the input signal is greater than 175 mVp-p, LOS will be deasserted. Outside of these ranges, the LOS indication is undefined. |
Other functions can be observed on LOSB real-time, configured via MDIO | |||
During device reset (RESET_N asserted low) this pin is driven low. During pin based power down (PDTRXB_N asserted low), this pin is floating. During register based power down (30.1.15 asserted high), this pin is floating. | |||
It is highly recommended that LOSB be brought to easily accessible point on the application board (header), in the event that debug is required. | |||
LS_OK_IN_B | P6 | Input LVCMOS 1.5V/1.8V VDDO3 |
Channel B Receive Lane Alignment Status Indicator. Lane alignment status signal received from a Lane Alignment Slave on the link partner device. Valid in 10G General Purpose Serdes Mode. LS_OK_IN_B=0: Channel B Receive lanes not aligned. LS_OK_IN_B=1: Channel B Receive lanes aligned |
LS_OK_OUT_B | N6 | Output LVCMOS 1.5V/1.8V VDDO3 40Ω Driver |
Channel B Transmit Lane Alignment Status Indicator. Lane alignment status signal sent to a Lane Alignment Master on the link partner device. Valid in 10G General Purpose Serdes Mode. LS_OK_OUT_B=0: Channel B Transmit lanes not aligned. LS_OK_OUT_B=1: Channel B Transmit lanes aligned. |
PDTRXB_N | P5 | Input LVCMOS 1.5V/1.8V VDDO1 |
Transceiver Power Down. When this pin is held low (asserted), Channel B is placed in power down mode. When deasserted, Channel B operates normally. After deassertion, a software data path reset should be issued through the MDIO interface. |
CHANNEL C | |||
HSTXCP HSTXCN |
A14 A15 |
Output CML VDDA_HS |
High Speed Transmit Channel C Output. HSTXCP and HSTXCN comprise the high speed side transmit direction Channel C differential serial output signal. During device reset (RESET_N asserted low) these pins are driven differential zero. These CML outputs must be AC coupled. |
HSRXCP HSRXCN |
A12 A11 |
Input CML VDDA_HS |
High Speed Receive Channel C Input. HSRXCP and HSRXCN comprise the high speed side receive direction Channel C differential serial input signal. These CML input signals must be AC coupled. |
INC[3:0]P/N | H18/G18 E18/D18 C17/B17 B18/A18 |
Input CML VDDA_LS |
Low Speed Channel C Inputs. INCP and INCN comprise the low speed side transmit direction Channel C differential input signals. These signals must be AC coupled. |
OUTC[3:0]P/N | J17/K17 H16/J16 F15/G15 D16/E16 |
Output CML VDDA_LS |
Low Speed Channel C Outputs. OUTCP and OUTCN comprise the low speed side receive direction Channel C differential output signals. During device reset (RESET_N asserted low) these pins are driven differential zero. These signals must be AC coupled. |
LOSC | D14 | Output LVCMOS 1.5V/1.8V VDDO1 40Ω Driver |
Channel C Receive Loss Of Signal (LOS) Indicator.
LOSC=0: Signal detected. LOSC=1: Loss of signal. Loss of signal detection is based on the input signal level. When HSRXCP/N has a differential input signal swing of ≤65 mVpp, LOSC will be asserted (if enabled). If the input signal is greater than 175 mVp-p, LOS will be deasserted. Outside of these ranges, the LOS indication is undefined. |
Other functions can be observed on LOSC real-time, configured via MDIO | |||
During device reset (RESET_N asserted low) this pin is driven low. During pin based power down (PDTRXC_N asserted low), this pin is floating. During register based power down (30.1.15 asserted high), this pin is floating. | |||
It is highly recommended that LOSC be brought to easily accessible point on the application board (header), in the event that debug is required. | |||
LS_OK_IN_C | F12 | Input LVCMOS 1.5V/1.8V VDDO1 |
Channel C Receive Lane Alignment Status Indicator.
Lane alignment status signal received from a Lane Alignment Slave on the link partner device. Valid in 10G General Purpose Serdes Mode. LS_OK_IN_C=0: Channel C Receive lanes not aligned. LS_OK_IN_C=1: Channel C Receive lanes aligned |
LS_OK_OUT_C | F13 | Output LVCMOS 1.5V/1.8V VDDO1 40Ω Driver |
Channel C Transmit Lane Alignment Status Indicator.
Lane alignment status signal sent to a Lane Alignment Master on the link partner device. Valid in 10G General Purpose Serdes Mode. LS_OK_OUT_C=0: Channel C Transmit lanes not aligned. LS_OK_OUT_C=1: Channel C Transmit lanes aligned. |
PDTRXC_N | D13 | Input LVCMOS 1.5V/1.8V VDDO1 |
Transceiver Power Down. When this pin is held low (asserted), Channel C is placed in power down mode. When deasserted, Channel C operates normally. After deassertion, a software data path reset should be issued through the MDIO interface. |
CHANNEL D | |||
HSTXDP HSTXDN |
V11 V10 |
Output CML VDDA_HS |
High Speed Transmit Channel D Output. HSTXDP and HSTXDN comprise the high speed side transmit direction Channel D differential serial output signal. During device reset (RESET_N asserted low) these pins are driven differential zero. These CML outputs must be AC coupled. |
HSRXDP HSRXDN |
V13 V14 |
Input CML VDDA_HS |
High Speed Receive Channel D Input. HSRXDP and HSRXDN comprise the high speed side receive direction Channel D differential serial input signal. These CML input signals must be AC coupled. |
IND[3:0]P/N | V16/V17 U17/U18 R18/P18 M18/L18 |
Input CML VDDA_LS |
Low Speed Channel D Inputs. INDP and INDN comprise the low speed side transmit direction Channel D differential input signals. These signals must be AC coupled. |
OUTD[3:0]P/N | T16/R16 R15/P15 N16/M16 L15/K15 |
Output CML VDDA_LS |
Low Speed Channel D Outputs. OUTDP and OUTDN comprise the low speed side receive direction Channel D differential output signals. During device reset (RESET_N asserted low) these pins are driven differential zero. These signals must be AC coupled. |
LOSD | R13 | Output LVCMOS 1.5V/1.8V VDDO2 40Ω Driver |
Channel D Receive Loss Of Signal (LOS) Indicator.
LOSD=0: Signal detected. LOSD=1: Loss of signal. Loss of signal detection is based on the input signal level. When HSRXDP/N has a differential input signal swing of ≤65 mVpp, LOSD will be asserted (if enabled). If the input signal is greater than 175 mVp-p, LOS will be deasserted. Outside of these ranges, the LOS indication is undefined. |
Other functions can be observed on LOSD real-time, configured via MDIO. | |||
During device reset (RESET_N asserted low) this pin is driven low. During pin based power down (PDTRXD_N asserted low), this pin is floating. During register based power down (30.1.15 asserted high), this pin is floating. |
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It is highly recommended that LOSD be brought to easily accessible point on the application board (header), in the event that debug is required. | |||
LS_OK_IN_D | K13 | Input LVCMOS 1.5V/1.8V VDDO2 |
Channel D Receive Lane Alignment Status Indicator.
Lane alignment status signal received from a Lane Alignment Slave on the link partner device. LS_OK_IN_D=0: Channel D Receive lanes not aligned. LS_OK_IN_D=1: Channel D Receive lanes aligned |
LS_OK_OUT_D | N13 | Output LVCMOS 1.5V/1.8V VDDO2 40Ω Driver |
Channel D Transmit Lane Alignment Status Indicator.
Lane alignment status signal sent to a Lane Alignment Master on the link partner device. LS_OK_OUT_D=0: Channel D Transmit lanes not aligned. LS_OK_OUT_D=1: Channel D Transmit lanes aligned. |
PDTRXD_N | P13 | Input LVCMOS 1.5V/1.8V VDDO2 |
Transceiver Power Down. When this pin is held low (asserted), Channel D is placed in power down mode. When deasserted, Channel D operates normally. After deassertion, a software data path reset should be issued through the MDIO interface. |
REFERENCE CLOCKS, OUTPUT CLOCKS, AND CONTROL AND MONITORING SIGNALS | |||
REFCLK0P/N | T5 T4 |
Input LVDS/ LVPECL DVDD |
Reference Clock Input Zero. This differential input is a clock signal used as a reference to channels A, B, C, or D. The reference clock selection is done through MDIO or the REFCLK_SEL pin. This input signal must be AC coupled. If unused, REFCLK0P/N should be pulled down to GND through a shared 100 Ω resistor. |
REFCLK1P/N | C15 C14 |
Input LVDS/ LVPECL DVDD |
Reference Clock Input One. This differential input is a clock signal used as a reference to channels A, B, C, or D. The reference clock selection is done through MDIO or the REFCLK_SEL pin. This input signal must be AC coupled. If unused, REFCLK1P/N should be pulled down to GND through a shared 100 Ω resistor. |
HSRXA_CLKOUTP/N HSRXB_CLKOUTP/N HSRXC_CLKOUTP/N HSRXD_CLKOUTP/N |
D8/D7 R7/R8 D12/D11 R11/R12 |
Output CML DVDD |
High Speed Side Recovered Byte Output Clock. By default, these outputs are disabled. When enabled they output the high speed side Channel A/B/C/D recovered byte clocks (high speed line rate divided by 16 or 20). Optionally they can be configured to output the VCO clock divided by 2. (Note: For full rates, VCO/2 pre divided clocks will be equivalent to the line rate divided by 8, for sub-rates, VCO/2 pre divided clocks will be equivalent to the line rate divided by 4) |
Additional MDIO-selectable divide ratios of 1, 2, 4, 5, 8, 10, 16, 20, and 25 are available. See Figure 5-35 for more information. | |||
These CML outputs must be AC coupled. | |||
During device reset (RESET_N asserted low), pin-based power down (PDTRXA_N, PDTRXB_N, PDTRXC_N, and PDTRXD_N asserted low), or register-based power down (30.1.15 asserted high per channel), these pins are floating. | |||
HSTX0_CLKOUTP/N HSTX1_CLKOUTP/N |
C6/C5 T10/T9 |
Output CML DVDD |
High Speed Side Transmit Output Clock. By default, these outputs are disabled. When enabled, they can be configured to output the high speed side transmit clock of any of the four channels. Additional MDIO-selectable divide ratios of 1, 2, 4, 5, 8, 10, 16, 20, and 25 are available. See Figure 5-35 for more information. |
These CML outputs must be AC coupled. | |||
During device reset (RESET_N asserted low), pin-based power down (PDTRXA_N, PDTRXB_N, PDTRXC_N, and PDTRXD_N asserted low), or register-based power down (30.1.15 asserted high on all channels), these pins are floating. | |||
LS0_CLKOUTP/N LS1_CLKOUTP/N |
C9/C10 T13/T14 |
Output CML DVDD |
Low Speed Side Output Clock. By default, these outputs are disabled. When enabled, they can be configured to output the low speed side transmit byte clock or recovered byte clock (low speed line rate divided by 10) of any of the four channels. Additional MDIO-selectable divide ratios of 1, 2, 4, 5, 8, 10, 16, 20, and 25 are available. See Figure 5-35 for more information. |
These CML outputs must be AC coupled. | |||
During device reset (RESET_N asserted low), pin-based power down (PDTRXA_N, PDTRXB_N, PDTRXC_N, and PDTRXD_N asserted low), or register-based power down (30.1.15 asserted high on all channels), these pins are floating. | |||
REFCLK_SEL | E7 | Input LVCMOS 1.5V/1.8V VDDO0 |
Reference Clock Select. This input, when low, selects REFCLK0P/N as the reference clock to all the SERDES channels. When high, REFCLK1P/N is selected as the reference clock to all the SERDES channels. If software control is desired (register bit 30.1.1), this input signal should be tied low. With software control, the reference clock for each channel can be independently selected. See Figure 5-34 for more information. Default reference clock for all the channels is REFCLK0P/N. |
PRBSEN | E5 | Input LVCMOS 1.5V/1.8V VDDO0 |
Enable PRBS: When this pin is asserted high, the internal PRBS generator and verifier circuits are enabled on both transmit and receive data paths on high speed and low speed sides of all the channels. |
The PRBS 231-1 pattern is selected by default, and can be changed through MDIO. | |||
For more details, see the test mode descriptions for the various operating modes. | |||
PRBS_PASS | G6 | Output LVCMOS 1.5V/1.8V VDDO0 40Ω Driver |
Receive PRBS Error Free (Pass) Indicator.
When PRBS test is enabled (PRBSEN=1): PRBS_PASS=1 indicates that PRBS pattern reception is error free. PRBS_PASS=0 indicates that a PRBS error is detected. The channel, high speed or low speed side, and lane (for low speed side) that this signal refers to is chosen through MDIO. |
During device reset (RESET_N asserted low) this pin is driven high. During pin based power down (PDTRXA_N, PDTRXB_N, PDTRXC_N, and PDTRXD_N asserted low), this pin is floating. During register based power down, this pin is floating. |
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It is highly recommended that PRBS_PASS be brought to easily accessible point on the application board (header), in the event that debug is required. | |||
ST | T12 | Input LVCMOS 1.5V/1.8V VDDO2 |
MDIO Select. Used to select Clause 22 (=1) or Clause 45 (=0) operation. Note that selecting clause 22 will impact mode availability. See MODE_SEL. |
A hard or soft reset must be applied after a change of state occurs on this input signal. | |||
MODE_SEL | P11 | Input LVCMOS 1.5V/1.8V VDDO2 |
Device Operating Mode Select.
Used together with ST pin to select device operating mode. See Table 5-13 for details. |
PRTAD[4:0] | M5 N14 P12 F14 N12 |
Input LVCMOS 1.5V/1.8V VDDO[3:1] |
MDIO Port Address. Used to select the MDIO port address. |
PRTAD[4:2] selects the MDIO port address. Selecting a unique PRTAD[4:2] per TLK10034 device allows 8 TLK10034 devices per MDIO bus. Each channel can be accessed by setting the appropriate port address field within the serial interface protocol transaction. | |||
The TLK10034 will respond if the 3 MSB’s of the port address field on MDIO protocol (PA[4:2]) matches PRTAD[4:2]. If PA[1:0] = 2’b00, TLK10034 Channel A will respond. If PA[1:0] = 2’b01, TLK10034 Channel B will respond. If PA[1:0] = 2’b10, TLK10034 Channel C will respond. If PA[1:0] = 2’b11, TLK10034 Channel D will respond. |
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PRTAD1 is not needed for device addressing, but shares functionality with the stopwatch latency timer function. PRTAD0 is not used functionally, but is present for device testability and compatibility with other devices in the family of products. PRTAD0 should be grounded on the application board. | |||
RESET_N | F8 | Input LVCMOS 1.5V/1.8V VDDO0 |
Low True Device Reset. RESET_N must be held asserted (low logic level) for at least 10us after device power stabilization. |
MDC | G5 | Input LVCMOS with Hysteresis 1.5V/1.8V VDDO0 |
MDIO Clock Input. Clock input for the MDIO interface. Note that an external pullup is generally not required on MDC except if driven by an open-drain/open-collector clock source. |
MDIO | F5 | Input/ Output LVCMOS 1.5V/1.8V VDDO0 25Ω Driver |
MDIO Data I/O. MDIO interface data input/output signal for the MDIO interface. This signal must be externally pulled up to VDDO using a 2kΩ resistor. |
During device reset (RESET_N asserted low) this pin is floating. During software initiated power down the management interface remains active for control register writes and reads. Certain status bits will not be deterministic as their generating clock source may be disabled as a result of asserting either power down input signal. During pin based power down (PDTRXA_N, PDTRXB_N, PDTRXC_N, and PDTRXD_N asserted low), this pin is floating. During register based power down (30.1.15 asserted high all channels), this pin is driven normally. | |||
TDI | E12 | Input LVCMOS 1.5V/1.8V VDDO1 (Internal Pullup) |
JTAG Input Data. TDI is used to serially shift test data and test instructions into the device during the operation of the test port. In system applications where JTAG is not implemented, this input signal may be left floating. During pin based power down (PDTRXA_N, PDTRXB_N, PDTRXC_N, and PDTRXD_N asserted low), this pin is not pulled up. During register based power down (30.1.15 asserted high all channels), this pin is pulled up normally. |
TDO | G14 | Output LVCMOS 1.5V/1.8V VDDO1 50Ω Driver |
JTAG Output Data. TDO is used to serially shift test data and test instructions out of the device during operation of the test port. When the JTAG port is not in use, TDO is in a high impedance state. During device reset (RESET_N asserted low) this pin is floating. During pin based power down (PDTRXA_N, PDTRXB_N, PDTRXC_N, and PDTRXD_N asserted low), this pin is floating. During register based power down (30.1.15 asserted high all channels), this pin is floating. |
TMS | E14 | Input LVCMOS 1.5V/1.8V VDDO1 (Internal Pullup) |
JTAG Mode Select. TMS is used to control the state of the internal test-port controller. In system applications where JTAG is not implemented, this input signal can be left unconnected. During pin based power down (PDTRXA_N, PDTRXB_N, PDTRXC_N, and PDTRXD_N asserted low), this pin is not pulled up. During register based power down (30.1.15 asserted high all channels), this pin is pulled up normally. |
TCK | E13 | Input LVCMOS with Hysteresis 1.5V/1.8V VDDO1 |
JTAG Clock. TCK is used to clock state information and test data into and out of the device during boundary scan operation. In system applications where JTAG is not implemented, this input signal should be grounded. |
TRST_N | H13 | Input LVCMOS 1.5V/1.8V VDDO1 (Internal Pulldown) |
JTAG Test Reset. TRST_N is used to reset the JTAG logic into system operational mode. This input can be left unconnected in the application and is pulled down internally, disabling the JTAG circuitry. If JTAG is implemented on the application board, this signal should be deasserted (high) during JTAG system testing, and otherwise asserted (low) during normal operation mode. During pin based power down (PDTRXA_N, PDTRXB_N, PDTRXC_N, and PDTRXD_N asserted low), this pin is not pulled down. During register based power down (30.1.15 asserted high all channels), this pin is pulled down normally. |
TESTEN | C8 | Input LVCMOS 1.5V/1.8V VDDO0 |
Test Enable. This signal is used during the device manufacturing process. It should be grounded through a resistor in the device application board. The application board should allow the flexibility of easily reworking this signal to a high level if device debug is necessary (by including an uninstalled resistor to VDDO). |
GPI[2:0] | M14 P14 D5 |
Input LVCMOS .5V/1.8V VDDO0,2 |
General Purpose Input. This signal is used during the device manufacturing process. It should be grounded through a resistor on the device application board. The application board should also allow the flexibility of easily reworking this signal to a high level if device debug is necessary (by including an uninstalled resistor to VDDO). |
AMUXA_LS/HS | E2 B8 |
Analog I/O | Analog Testability I/O. This signal is used during the device manufacturing process. It should be left unconnected in the device application. |
AMUXB_LS/HS | P2 U8 |
Analog I/O | Analog Testability I/O. This signal is used during the device manufacturing process. It should be left unconnected in the device application. |
AMUXC_LS/HS | E17 B10 |
Analog I/O | Analog Testability I/O. This signal is used during the device manufacturing process. It should be left unconnected in the device application. |
AMUXD_LS/HS | P17 U10 |
Analog I/O | Analog Testability I/O. This signal is used during the device manufacturing process. It should be left unconnected in the device application. |
TERMINAL | TYPE | DESCRIPTION | |
---|---|---|---|
SIGNAL | BGA | ||
VDDA[1:0]_LS/HS | H2, H3, L2, M3, F9, E10, F11, G16, H17, L16, L17, N9, P10, N11 | Power | SERDES Analog Power.
VDDA_LS and VDDA_HS provide supply voltage for the analog circuits on the low-speed and high-speed sides respectively. 1.0V nominal. Can be tied together on the application board. |
VDDT[1:0]_LS/HS | J5, K5, E8, J14, K14, P8 | Power | SERDES Analog Power.
VDDT_LS and VDDT_HS provide termination and supply voltage for the analog circuits on the low-speed and high-speed sides respectively. 1.0V nominal. Can be tied together on the application board. |
VDDD | H8, J8, K8, L8, M9, G10, H11, J11, K11, L11 | Power | SERDES Digital Power.
VDDD provides supply voltage for the digital circuits internal to the SERDES. 1.0V nominal. |
DVDD | H7, K7, L7, H9, J9, L9, H10, K10, L10, H12, J12, L12 | Power | Digital Core Power.
DVDD provides supply voltage to the digital core. 1.0V nominal. |
VDDRA_LS/HS | G4 B6 |
Power | SERDES Analog Regulator Power.
VDDRA_LS and VDDRA_HS provide supply voltage for the internal PLL regulator for Channel A low speed and high speed sides respectively. 1.5V or 1.8V nominal. |
VDDRB_LS/HS | K4 U6 |
Power | SERDES Analog Regulator Power
VDDRB_LS and VDDRB_HS provide supply voltage for the internal PLL regulator for Channel B low speed and high speed sides respectively. 1.5V or 1.8V nominal. |
VDDRC_LS/HS | J15 B12 |
Power | SERDES Analog Regulator Power.
VDDRC_LS and VDDRC_HS provide supply voltage for the internal PLL regulator for Channel C low speed and high speed sides respectively. 1.5V or 1.8V nominal. |
VDDRD_LS/HS | M15 U12 |
Power | SERDES Analog Regulator Power
VDDRD_LS and VDDRD_HS provide supply voltage for the internal PLL regulator for Channel D low speed and high speed sides respectively. 1.5V or 1.8V nominal. |
VDDO[3:0] | M7 M12 G12 G7 |
Power | LVCMOS I/O Power.
VDDO0[3:0] and VDDO1 provide supply voltage for the LVCMOS inputs and outputs. 1.5V or 1.8V nominal. Can be tied together on the application board. |
VPP | N7 | Power | Factory Program Voltage.
Used during device manufacturing. The application must connect this power supply directly to DVDD. |
VSS | A1, A4, A7, A10, A13, A16, A17, B3, B4, B5, B7, B9, B11, B13, B14, B15, B16, C1, C2, C4, C7, C11, C12, C13, C16, C18, D2, D9, D10, D15, D17, E3, E9, E11, E15, F1, F2, F4, F7, F10, F16, F17, F18, G2, G8, G9, G11, G13, G17, H5, H6, H14, H15, J1, J3, J7, J10, J13, J18, K1, K6, K9, K12, K16, K18, L4, L5, L6, L13, L14, M2, M6, M8, M10, M11, M13, M17, N1, N2, N3, N5, N8, N10, N15, N17, N18, P4, P9, P16, R2, R4, R5, R6, R9, R10, R14, R17, T1, T3, T6, T7, T8, T11, T15, T17, T18, U3, U4, U5, U7, U9, U11, U13, U14, U15, U16, V2, V3, V6, V9, V12, V15, V18 | Ground | Ground.
Common analog and digital ground. |