SLLSEB8C August   2012  – April  2016 TLK105 , TLK106

PRODUCTION DATA.  

  1. 1  Introduction
    1. 1.1 Features
    2. 1.2 Applications
    3. 1.3 Device Overview
      1. 1.3.1 Electrostatic Discharge Caution
  2. 2 Pin Descriptions
    1. 2.1 Pin Layout
    2. 2.2 Serial Management Interface (SMI)
    3. 2.3 MAC Data Interface
    4. 2.4 10Mbs and 100Mbs PMD Interface
    5. 2.5 Clock Interface
    6. 2.6 LED Interface
    7. 2.7 Reset and Power Down
    8. 2.8 Power and Bias Connections
  3. 3 Hardware Configuration
    1. 3.1  Bootstrap Configuration
    2. 3.2  Power Supply Configuration
      1. 3.2.1 Single Supply Operation
      2. 3.2.2 Dual Supply Operation
      3. 3.2.3 Variable IO Voltage
    3. 3.3  IO Pins Hi-Z State During Reset
    4. 3.4  Auto-Negotiation
    5. 3.5  Auto-MDIX
    6. 3.6  MII Isolate Mode
    7. 3.7  PHY Address
    8. 3.8  LED Interface
    9. 3.9  Loopback Functionality
      1. 3.9.1 Near-End Loopback
      2. 3.9.2 Far-End Loopback
    10. 3.10 BIST
    11. 3.11 Cable Diagnostics
      1. 3.11.1 TDR
      2. 3.11.2 ALCD
  4. 4 Interfaces
    1. 4.1 Media Independent Interface (MII)
    2. 4.2 Reduced Media Independent Interface (RMII)
    3. 4.3 Serial Management Interface
      1. 4.3.1 Extended Address Space Access
        1. 4.3.1.1 Write Address Operation
        2. 4.3.1.2 Read Address Operation
        3. 4.3.1.3 Write (no post increment) Operation
        4. 4.3.1.4 Read (no post increment) Operation
        5. 4.3.1.5 Write (post increment) Operation
        6. 4.3.1.6 Read (post increment) Operation
  5. 5 Architecture
    1. 5.1 100Base-TX Transmit Path
      1. 5.1.1 MII Transmit Error Code Forwarding
      2. 5.1.2 4-Bit to 5-Bit Encoding
      3. 5.1.3 Scrambler
      4. 5.1.4 NRZI and MLT-3 Encoding
      5. 5.1.5 Digital to Analog Converter
    2. 5.2 100Base-TX Receive Path
      1. 5.2.1  Analog Front End
      2. 5.2.2  Adaptive Equalizer
      3. 5.2.3  Baseline Wander Correction
      4. 5.2.4  NRZI and MLT-3 Decoding
      5. 5.2.5  Descrambler
      6. 5.2.6  5B/4B Decoder and Nibble Alignment
      7. 5.2.7  Timing Loop and Clock Recovery
      8. 5.2.8  Phase-Locked Loops (PLL)
      9. 5.2.9  Link Monitor
      10. 5.2.10 Signal Detect
      11. 5.2.11 Bad SSD Detection
    3. 5.3 10Base-T Receive Path
      1. 5.3.1 10M Receive Input and Squelch
      2. 5.3.2 Collision Detection
      3. 5.3.3 Carrier Sense
      4. 5.3.4 Jabber Function
      5. 5.3.5 Automatic Link Polarity Detection and Correction
      6. 5.3.6 10Base-T Transmit and Receive Filtering
      7. 5.3.7 10Base-T Operational Modes
    4. 5.4 Auto Negotiation
      1. 5.4.1 Operation
      2. 5.4.2 Initialization and Restart
      3. 5.4.3 Next Page Support
    5. 5.5 Link Down Functionality
  6. 6 Reset and Power Down Operation
    1. 6.1 Hardware Reset
    2. 6.2 Software Reset
    3. 6.3 Power Down/Interrupt
      1. 6.3.1 Power Down Control Mode
      2. 6.3.2 Interrupt Mechanisms
    4. 6.4 Power Save Modes
  7. 7 Design Guidelines
    1. 7.1 TPI Network Circuit
    2. 7.2 Clock In (XI) Requirements
      1. 7.2.1 Oscillator
      2. 7.2.2 Crystal
    3. 7.3 Thermal Vias Recommendation
  8. 8 Register Block
    1. 8.1 Register Definition
      1. 8.1.1  Basic Mode Control Register (BMCR)
      2. 8.1.2  Basic Mode Status Register (BMSR)
      3. 8.1.3  PHY Identifier Register 1 (PHYIDR1)
      4. 8.1.4  PHY Identifier Register 2 (PHYIDR2)
      5. 8.1.5  Auto-Negotiation Advertisement Register (ANAR)
      6. 8.1.6  Auto-Negotiation Link Partner Ability Register (ANLPAR) (BASE Page)
      7. 8.1.7  Auto-Negotiate Expansion Register (ANER)
      8. 8.1.8  Auto-Negotiate Next Page Transmit Register (ANNPTR)
      9. 8.1.9  Auto-Negotiation Link Partner Ability Next Page Register (ANLNPTR)
      10. 8.1.10 Control register 1 (CR1)
      11. 8.1.11 Control register 2 (CR2)
      12. 8.1.12 Control Register 3 (CR3)
      13. 8.1.13 Extended Register Addressing
        1. 8.1.13.1 Register Control Register (REGCR)
        2. 8.1.13.2 Address or Data Register (ADDAR)
      14. 8.1.14 PHY Status Register (PHYSTS)
      15. 8.1.15 PHY Specific Control Register (PHYSCR)
      16. 8.1.16 MII Interrupt Status Register 1 (MISR1)
      17. 8.1.17 MII Interrupt Status Register 2 (MISR2)
      18. 8.1.18 False Carrier Sense Counter Register (FCSCR)
      19. 8.1.19 Receiver Error Counter Register (RECR)
      20. 8.1.20 BIST Control Register (BISCR)
      21. 8.1.21 RMII Control and Status Register (RCSR)
      22. 8.1.22 LED Control Register (LEDCR)
      23. 8.1.23 PHY Control Register (PHYCR)
      24. 8.1.24 10Base-T Status/Control Register (10BTSCR)
      25. 8.1.25 BIST Control and Status Register 1 (BICSR1)
      26. 8.1.26 BIST Control and Status Register2 (BICSR2)
    2. 8.2 Cable Diagnostic Control Register (CDCR)
    3. 8.3 PHY Reset Control Register (PHYRCR)
    4. 8.4 Compliance Test register (COMPTR)
    5. 8.5 TX_CLK Phase Shift Register (TXCPSR)
    6. 8.6 Power Back Off Control Register (PWRBOCR)
    7. 8.7 Voltage Regulator Control Register (VRCR)
    8. 8.8 Cable Diagnostic Configuration/Result Registers
      1. 8.8.1  ALCD Control and Results 1 (ALCDRR1)
      2. 8.8.2  Cable Diagnostic Specific Control Registers (CDSCR1 - CDSCR4)
      3. 8.8.3  Cable Diagnostic Location Results Register 1 (CDLRR1)
      4. 8.8.4  Cable Diagnostic Location Results Register 2 (CDLRR2)
      5. 8.8.5  Cable Diagnostic Location Results Register 3 (DDLRR3)
      6. 8.8.6  Cable Diagnostic Location Results Register 4 (CDLRR4)
      7. 8.8.7  Cable Diagnostic Location Results Register 5 (CDLRR5)
      8. 8.8.8  Cable Diagnostic Amplitude Results Register 1 (CDARR1)
      9. 8.8.9  Cable Diagnostic Amplitude Results Register 2 (CDARR2)
      10. 8.8.10 Cable Diagnostic Amplitude Results Register 3 (CDARR3)
      11. 8.8.11 Cable Diagnostic Amplitude Results Register 4 (CDARR4)
      12. 8.8.12 Cable Diagnostic Amplitude Results Register 5 (CDARR5)
      13. 8.8.13 Cable Diagnostic General Results Register (CDGRR)
      14. 8.8.14 ALCD Control and Results 2 (ALCDRR2)
  9. 9 Electrical Specifications
    1. 9.1 Absolute Maximum Ratings
    2. 9.2 ESD Ratings
    3. 9.3 Recommended Operating Conditions
    4. 9.4 145
      1. 9.4.1 TLK105 32-Pin Industrial Device (85°C) Thermal Characteristics
    5. 9.5 TLK106 32-Pin Extended Temperature (105°C) Device Thermal Characteristics
    6. 9.6 DC Characteristics, VDD_IO
    7. 9.7 DC Characteristics
    8. 9.8 Power Supply Characteristics
      1. 9.8.1 Active Power, Single Supply Operation
      2. 9.8.2 Active Power, Dual Supply Operation
      3. 9.8.3 Power-Down Power
    9. 9.9 AC Specifications
      1. 9.9.1  Power Up Timing
      2. 9.9.2  Reset Timing
      3. 9.9.3  MII Serial Management Timing
      4. 9.9.4  100Mb/s MII Transmit Timing
      5. 9.9.5  100Mb/s MII Receive Timing
      6. 9.9.6  100Base-TX Transmit Packet Latency Timing
      7. 9.9.7  100Base-TX Transmit Packet Deassertion Timing
      8. 9.9.8  100Base-TX Transmit Timing (tR/F and Jitter)
      9. 9.9.9  100Base-TX Receive Packet Latency Timing
      10. 9.9.10 100Base-TX Receive Packet Deassertion Timing
      11. 9.9.11 10Mbs MII Transmit Timing
      12. 9.9.12 10Mb/s MII Receive Timing
      13. 9.9.13 10Base-T Transmit Timing (Start of Packet)
      14. 9.9.14 10Base-T Transmit Timing (End of Packet)
      15. 9.9.15 10Base-T Receive Timing (Start of Packet)
      16. 9.9.16 10Base-T Receive Timing (End of Packet)
      17. 9.9.17 10Mb/s Jabber Timing
      18. 9.9.18 10Base-T Normal Link Pulse Timing
      19. 9.9.19 Auto-Negotiation Fast Link Pulse (FLP) Timing
      20. 9.9.20 100Base-TX Signal Detect Timing
      21. 9.9.21 100Mbs Loopback Timing
      22. 9.9.22 10Mbs Internal Loopback Timing
      23. 9.9.23 RMII Transmit Timing
      24. 9.9.24 RMII Receive Timing
      25. 9.9.25 Isolation Timing
  10. 10Revision History

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • RHB|32
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7 Design Guidelines

7.1 TPI Network Circuit

Figure 7-1 shows the recommended circuit for a 10/100Mbs twisted pair interface. Common mode chokes on the device side of the transformer are required. Variations with PCB and component characteristics require that the application be tested to verify that the circuit meets the requirements of the intended application.

TLK105 TLK106 twist_pair_if_lls901_update_req.gif Figure 7-1 10/100Mbs Twisted Pair Interface

7.2 Clock In (XI) Requirements

The TLK10x supports an external CMOS-level oscillator source or an internal oscillator with an external crystal.

7.2.1 Oscillator

If an external clock source is used, XI should be tied to the clock source and XO should be left floating. The oscillator should use the same supply voltage as the VDD_IO supply. When operating in RMII, the oscillator supply voltage must be 3.3V or 2.5V.

7.2.2 Crystal

The use of a 25MHz, parallel, 20pF-load crystal is recommended if a crystal source is desired. Figure 7-2 shows a typical connection for a crystal resonator circuit. The load capacitor values will vary with the crystal vendors; check with the vendor for the recommended loads.

The oscillator circuit is designed to drive a parallel-resonance AT-cut crystal with a minimum drive level of 100μW and a maximum of 500μW. If a crystal is specified for a lower drive level, a current limiting resistor must be placed in series between XO and the crystal.

As a starting point for evaluating an oscillator circuit, if the requirements for the crystal are not known, set the values for CL1 and CL2 at 33pF, and R1 should be set at 0Ω. Specifications for a 25MHz crystal are listed in Table 7-3.

TLK105 TLK106 s0340-01_lls931.gif Figure 7-2 Crystal Oscillator Circuit

Table 7-1 25MHz Oscillator Specification

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Frequency 25 MHz
Frequency Tolerance Operational Temperature ±50 ppm
Frequency Stability 1 year aging ±50 ppm
Rise / Fall Time 10%–90% 8 nsec
Jitter (Short term) Cycle-to-cycle 50 psec
Jitter (Long term) Accumulative over 10 ms 1 nsec
Symmetry Duty Cycle 40% 60%
Load Capacitance 15 30 pF

Table 7-2 50MHz Oscillator Specification

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Frequency 50 MHz
Frequency Tolerance Operational Temperature ±50 ppm
Frequency Stability 1 year aging ±50 ppm
Rise / Fall Time 10%–90% 6 nsec
Jitter (Short term) Cycle-to-cycle 50 psec
Jitter (Long term) Accumulative over 10 ms 1 nsec
Symmetry Duty Cycle 40% 60%

Table 7-3 25MHz Crystal Specification

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Frequency 25 MHz
Frequency Tolerance Operational Temperature ±50 ppm
At 25°C ±50 ppm
Frequency Stability 1 year aging ±5 ppm
Load Capacitance 10 40 pF

7.3 Thermal Vias Recommendation

The following thermal via guidelines apply to DOWN_PAD, pin 33:

  1. Thermal via size = 0.2mm
  2. Recommend 4 vias
  3. Vias have a center to center separation of 2mm.

Adherence to this guideline is required to achieve the intended operating temperature range of the device. Figure 7-3 illustrates an example layout.

TLK105 TLK106 example_layout_llseb8.gifFigure 7-3 Example Layout