SLLSEB8C August 2012 – April 2016 TLK105 , TLK106
PRODUCTION DATA.
Refer to the PDF data sheet for device specific package drawings
The TLK10x pins fall into the following interface categories (subsequent sections describe each interface):
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Note: Configuration pin option. See Section 3.1 for Jumper Definitions.
The definitions below define the functionality of each pin.
Type: I | Input | Type: OD | Open Drain | |
Type: O | Output | Type: PD, PU | Internal Pulldown/Pullup | |
Type: I/O | Input/Output | Type: S | Configuration Pin (All configuration pins have weak internal pullups or pulldowns. Use an external 2.2kΩ resistor if you need a different default value. See Section 3.1 for details.) |
This document describes signals that take on different names depending on configuration. In such cases, the different names are placed together and separated by slash (/) characters. For example, "RXD_3 / PHYAD4". Active low signals are represented by overbars.
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PIN | TYPE | DESCRIPTION | |
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NAME | NO. | ||
MDC | 20 | I | MANAGEMENT DATA CLOCK: Clock signal for the management data input/output (MDIO) interface. The maximum MDC rate is 25MHz; there is no minimum MDC rate. MDC is not required to be synchronous to the TX_CLK or the RX_CLK. |
MDIO | 19 | I/O | MANAGEMENT DATA I/O: Bidirectional command / data signal synchronized to MDC. Either the local controller or the TLK10x may drive the MDIO signal. This pin requires a pull-up resistor with value 2.2kΩ. |
PIN | TYPE | DESCRIPTION | |
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NAME | NO. | ||
TX_CLK | 2 | O, PD |
MII TRANSMIT CLOCK: MII Transmit Clock provides the 25MHz or 2.5MHz reference clock depending on the speed. Note that in MII mode, this clock has constant phase referenced to REF_CLK. Applications requiring such constant phase may use this feature. Unused in RMII mode. In RMII, X1 reference clock is used as the clock for both transmit and receive. |
TX_EN | 3 | I, PD | TRANSMIT ENABLE: TX_EN is presented on the rising edge of the TX_CLK . TX_EN indicates the presence of valid data inputs on TXD[3:0] in MII mode, and on TXD [1:0] in the RMII mode. TX_EN is an active high signal. |
TXD_0 TXD_1 TXD_2 TXD_3 |
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5 6 7 |
I, PD | TRANSMIT DATA: In MII mode, the transmit data nibble received from the MAC is synchronous to the rising edge of the TX_CLK signal. In RMII mode, TXD [1:0] received from the MAC is synchronous to the 50MHz reference clock on XI. |
RX_CLK | 25 | O | RECEIVE CLOCK: In MII mode it is the receive clock that provides either a 25MHz or 2.5MHz reference clock, depending on the speed, that is derived from the received data stream. |
RX_DV / MII_MODE | 26 | S, O, PD | RECEIVE DATA VALID: This pin indicates valid data is present on the RXD [3:0] for MII mode or on RXD [1:0] for RMII mode, independently from Carrier Sense. |
RX_ER / AMDIX_EN | 28 | S, O, PU | RECEIVE ERROR: This pin indicates that an error symbol has been detected within a received packet in both MII and RMII mode. In MII mode, RX_ER is asserted high synchronously to RX_CLK and in RMII mode, synchronously to XI (50MHz). This pin is not required to be used by the MAC, in either MII or RMII, because the PHY is corrupting data on a receive error. |
RXD_0 / PHYAD1 RXD_1 / PHYAD2 RXD_2 / PHYAD3 RXD_3 / PHYAD4 |
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31 32 1 |
S, O, PD | RECEIVE DATA: Symbols received on the cable are decoded and presented on these pins synchronous to RX_CLK. They contain valid data when RX_DV is asserted. A nibble RXD [3:0] is received in the MII mode and 2-bits RXD[1:0] is received in the RMII Mode. PHY address pins PHYAD[4:1] are multiplexed with RXD [3:0], and are pulled down. PHYAD0 (LSB of the address) is multiplexed with COL on pin 29, and is pulled up. If no external pullup/pulldown is present, the default address is 0x01. |
CRS / CRS_DV/ LED_CFG | 27 | S, O, PU |
CARRIER SENSE: In MII mode this pin is asserted high when the receive medium is non-idle. CARRIER SENSE/RECEIVE DATA VALID: In RMII mode, this pin combines the RMII Carrier and Receive Data Valid indications. |
COL / PHYAD0 | 29 | S, O, PU |
COLLISION DETECT: For MII mode in Full Duplex Mode this pin is always low. In 10Base-T/100Base-TX half-duplex modes, this pin is asserted HIGH only when both transmit and receive media are non-idle. This pin is not used in RMII mode. |
PIN | TYPE | DESCRIPTION | |
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NAME | NO. | ||
TD–, TD+ | 11, 12 | I/O | Differential common driver transmit output (PMD Output Pair): These differential outputs are automatically configured to either 10Base-T or 100Base-TX signaling. In Auto-MDIX mode of operation, this pair can be used as the Receive Input pair. These pins require 3.3V bias for operation. |
RD–, RD+ | 9, 10 | I/O | Differential receive input (PMD Input Pair): These differential inputs are automatically configured to accept either 100Base-TX or 10Base-T signaling. In Auto-MDIX mode of operation, this pair can be used as the Transmit Output pair. These pins require 3.3V bias for operation. |
PIN | TYPE | DESCRIPTION | ||
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NAME | NO. | |||
LED_LINK / AN_0 | 17 | S, O, PU | LED Pin to indicate status | |
Mode 1 | LINK Indication LED: Indicates the status of the link. When the link is good, the LED is ON. | |||
Mode 2 | ACT indication LED: Indicates transmit and receive activity in addition to the status of the Link. The LED is ON when Link is good. The LED blinks when the transmitter or receiver is active. |
PIN | TYPE | DESCRIPTION | |
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NAME | NO. | ||
RESET | 18 | I, PU | This pin is an active-low reset input that initializes or re-initializes all the internal registers of the TLK10x. Asserting this pin low for at least 1µs will force a reset process to occur. All jumper options are reinitialized as well. |
INT / PWDN | 8 | IO, OD, PU | Register access is required for this pin to be configured either as power down or as an interrupt. The default function of this pin is power down. |
When this pin is configured for a power down function, an active low signal on this pin places the device in power down mode. | |||
When this pin is configured as an interrupt pin, then this pin is asserted low when an interrupt condition occurs. The pin has an open-drain output with a weak internal pull-up. Some applications may require an external pull-up resistor. |
PIN | TYPE | DESCRIPTION | |
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NAME | NO. | ||
RBIAS | 16 | I | Bias Resistor Connection: Use a 4.87kΩ 1% resistor connected from RBIAS to GND. |
PFBOUT | 15 | O | Power Feedback Output: Place 10µf and 0.1μF capacitors (ceramic preferred) close to PFBOUT. |
In single-supply operation, connect this pin to PFBIN1 and PFBIN2 (pin 13 and pin 24). See Figure 3-1 for proper placement. | |||
In multiple supply operation, this pin is not used. | |||
PFBIN1 | 13 | I | Power Feedback Input: These pins are fed with power from PFBOUT (pin 15) in single supply operation. |
PFBIN2 | 24 | In multiple supply operation, connect a 1.55V external power supply to these pins. Connect a small capacitor of 0.1µF close to each pin. To power down the internal linear regulator, write to register 0x00d0. | |
VDD_IO | 21 | P | I/O 3.3V, 2.5V, or 1.8V Supply - For details, see Section 3.2.3 |
AVDD33 | 14 | P | Analog 3.3V power supply |
GND | Ground Pad | P | Ground Pad |