The TLK111 is a single-port Ethernet PHY for 10Base-T and 100Base TX signaling. This device integrates all the physical-layer functions needed to transmit and receive data on standard twisted-pair cables. The TLK111 supports the standard Media Independent Interface (MII) and Reduced Media Independent Interface (RMII) for direct connection to a Media Access Controller (MAC).
The TLK111 is designed for power-supply flexibility, and can operate with a single 3.3V power supply or with combinations of 3.3V and 1.55V power supplies for reduced power operation.
The TLK111 uses mixed-signal processing to perform equalization, data recovery, and error correction to achieve robust operation over CAT 5 twisted-pair wiring. This device not only meets the requirements of IEEE 802.3, but maintains high margins in terms of cross-talk and alien noise.
The TLK111 Ethernet PHY has a special Power Back Off mode to conserve power in systems with relatively short cables. This mode provides the flexibility to reduce system power when the system is not required to drive the standard IEEE 802.3 100m cable length, or the extended 150m, error-free cable reach of the TLK111. For more detail, see application note SLLA328.
The TLK111 pins fall into the following interface categories (subsequent sections describe each interface):
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Note: Configuration pin option. See Section 3.1 for Jumper Definitions.
The definitions below define the functionality of each pin.
Type: I | Input | Type: OD | Open Drain | |
Type: O | Output | Type: PD, PU | Internal Pulldown/Pullup | |
Type: I/O | Input/Output | Type: S | Configuration Pin (All configuration pins have weak internal pullups or pulldowns. Use an external 2.2kΩ resistor if you need a different default value. See Section 3.1 for details.) |
This document describes signals that take on different names depending on configuration. In such cases, the different names are placed together and separated by slash (/) characters. For example, "RXD_3 / PHYAD4". Active low signals are represented by overbars.
PIN | TYPE | DESCRIPTION | |
---|---|---|---|
NAME | NO. | ||
MDC | 31 | I | MANAGEMENT DATA CLOCK: Clock signal for the management data input/output (MDIO) interface. The maximum MDC rate is 25MHz; there is no minimum MDC rate. MDC is not required to be synchronous to the TX_CLK or the RX_CLK. |
MDIO | 30 | I/O | MANAGEMENT DATA I/O: Bidirectional command / data signal synchronized to MDC. Either the local controller or the TLK111 may drive the MDIO signal. This pin requires a pull-up resistor with value 2.2kΩ. |
PIN | TYPE | DESCRIPTION | |
---|---|---|---|
NAME | NO. | ||
TX_CLK | 1 | O, PD |
MII TRANSMIT CLOCK: MII Transmit Clock provides the 25MHz or 2.5MHz reference clock depending on the speed. Note that in MII mode, this clock has constant phase referenced to REF_CLK. Applications requiring such constant phase may use this feature. Unused in RMII mode. In RMII, X1 reference clock is used as the clock for both transmit and receive. |
TX_EN | 2 | I, PD | TRANSMIT ENABLE: TX_EN is presented on the rising edge of the TX_CLK . TX_EN indicates the presence of valid data inputs on TXD[3:0] in MII mode, and on TXD [1:0] in the RMII mode. TX_EN is an active high signal. |
TXD_0 TXD_1 TXD_2 TXD_3 |
3
4 5 6 |
I, PD | TRANSMIT DATA: In MII mode, the transmit data nibble received from the MAC is synchronous to the rising edge of the TX_CLK signal. In RMII mode, TXD [1:0] received from the MAC is synchronous to the 50MHz reference clock on XI. |
RX_CLK | 38 | O | RECEIVE CLOCK: In MII mode it is the receive clock that provides either a 25MHz or 2.5MHz reference clock, depending on the speed, that is derived from the received data stream. |
RX_DV / MII_MODE | 39 | S, O, PD | RECEIVE DATA VALID: This pin indicates valid data is present on the RXD [3:0] for MII mode or on RXD [1:0] for RMII mode, independently from Carrier Sense. |
RX_ER / AMDIX_EN | 41 | S, O, PU | RECEIVE ERROR: This pin indicates that an error symbol has been detected within a received packet in both MII and RMII mode. In MII mode, RX_ER is asserted high synchronously to RX_CLK and in RMII mode, synchronously to XI (50MHz). This pin is not required to be used by the MAC, in either MII or RMII, because the PHY is corrupting data on a receive error. |
RXD_0 / PHYAD1 RXD_1 / PHYAD2 RXD_2 / PHYAD3 RXD_3 / PHYAD4 |
43
44 45 46 |
S, O, PD | RECEIVE DATA: Symbols received on the cable are decoded and presented on these pins synchronous to RX_CLK. They contain valid data when RX_DV is asserted. A nibble RXD [3:0] is received in the MII mode and 2-bits RXD[1:0] is received in the RMII Mode. PHY address pins PHYAD[4:1] are multiplexed with RXD [3:0], and are pulled down. PHYAD0 (LSB of the address) is multiplexed with COL on pin 42, and is pulled up. If no external pullup/pulldown is present, the default address is 0x01. |
CRS / LED_CFG | 40 | S, O, PU |
CARRIER SENSE: In MII mode this pin is asserted high when the receive medium is non-idle. CARRIER SENSE/RECEIVE DATA VALID: In RMII mode, this pin combines the RMII Carrier and Receive Data Valid indications. |
COL / PHYAD0 | 42 | S, O, PU |
COLLISION DETECT: For MII mode in Full Duplex Mode this pin is always low. In 10Base-T/100Base-TX half-duplex modes, this pin is asserted HIGH only when both transmit and receive media are non-idle. This pin is not used in RMII mode. |
PIN | TYPE | DESCRIPTION | |
---|---|---|---|
NAME | NO. | ||
TD–, TD+ | 16, 17 | I/O | Differential common driver transmit output (PMD Output Pair): These differential outputs are automatically configured to either 10Base-T or 100Base-TX signaling. In Auto-MDIX mode of operation, this pair can be used as the Receive Input pair. These pins require 3.3V bias for operation. |
RD–, RD+ | 13, 14 | I/O | Differential receive input (PMD Input Pair): These differential inputs are automatically configured to accept either 100Base-TX or 10Base-T signaling. In Auto-MDIX mode of operation, this pair can be used as the Transmit Output pair. These pins require 3.3V bias for operation. |
PIN | TYPE | DESCRIPTION | |
---|---|---|---|
NAME | NO. | ||
XI | 34 | I | CRYSTAL/OSCILLATOR INPUT: |
MII reference clock: Reference clock. 25MHz ±50ppm-tolerance crystal reference or oscillator input. The device supports either an external crystal resonator connected across pins XI and XO, or an external CMOS-level oscillator source connected to pin XI only. | |||
RMII reference clock: Primary clock reference input for the RMII mode. The input must be connected to a 50MHz ±50ppm-tolerance CMOS-level oscillator source. | |||
XO | 33 | O | CRYSTAL OUTPUT: Reference Clock output. XO pin is used for crystal only. This pin should be left floating when an oscillator input is connected to XI. |
CLKOUT | 25 | O | CLOCK OUTPUT: In MII mode, this pin provides a 25 MHz clock output to the system. In RMII mode, this pin provides a 50MHz clock output. This feature allows other devices to use the reference clock from the TLK111 without requiring additional clock sources. |
PIN | TYPE | DESCRIPTION | ||
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NAME | NO. | |||
LED_LINK / AN_0 | 28 | S, O, PU | LED Pin to indicate status | |
Mode 1 | LINK Indication LED: Indicates the status of the link. When the link is good, the LED is ON. | |||
Mode 2 and Mode 3 | ACT indication LED: Indicates transmit and receive activity in addition to the status of the Link. The LED is ON when Link is good. The LED blinks when the transmitter or receiver is active. | |||
LED_SPEED / AN_1 | 27 | S, O, PU | LED Pin to indicate the speed of the link. SPEED Indication LED indicates whether the link is 100Mb/s or 10Mb/s. The LED is ON when the link speed is 100Mbs and OFF when it is 10Mbs. | |
LED_ACT / AN_EN | 26 | S, O, PU | LED Pin to indicate status. | |
Mode 1 | ACT indication LED: Indicates if there is any activity on the link. The LED is ON (pulse) when activity is present on either Transmit or Receive channel. | |||
Mode 2 | COL indication LED: Indicates collision detection. | |||
Mode 3 | may be programmed to DUPLEX Indication LED and indicates Full-duplex status. |
PIN | TYPE | DESCRIPTION | |
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NAME | NO. | ||
JTAG_TCK | 8 | I, PU | JTAG Test Clock: This pin has a weak internal pullup. |
JTAG_TDI | 12 | I, PU | JTAG Test Data Input: This pin has a weak internal pullup. |
JTAG_TDO | 9 | O | JTAG Test Data Output |
JTAG_TMS | 10 | I, PU | JTAG Test Mode Select: This pin has a weak internal pullup. |
JTAG_TRST | 11 | I, PU | JTAG Reset: This pin is an active-low asynchronous test reset with a weak internal pullup. |
PIN | TYPE | DESCRIPTION | |
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NAME | NO. | ||
RESET | 29 | I, PU | This pin is an active-low reset input that initializes or re-initializes all the internal registers of the TLK111. Asserting this pin low for at least 1µs will force a reset process to occur. All jumper options are reinitialized as well. |
INT / PWDN | 7 | IO, OD, PU | Register access is required for this pin to be configured either as power down or as an interrupt. The default function of this pin is power down. |
When this pin is configured for a power down function, an active low signal on this pin places the device in power down mode. | |||
When this pin is configured as an interrupt pin, then this pin is asserted low when an interrupt condition occurs. The pin has an open-drain output with a weak internal pull-up. Some applications may require an external pull-up resistor. |
PIN | TYPE | DESCRIPTION | |
---|---|---|---|
NAME | NO. | ||
RBIAS | 24 | I | Bias Resistor Connection: Use a 4.87kΩ 1% resistor connected from RBIAS to GND. |
PFBOUT | 23 | O | Power Feedback Output: Place 10µf and 0.1μF capacitors (ceramic preferred) close to PFBOUT. |
In single-supply operation, connect this pin to PFBIN1 and PFBIN2 (pin 18 and pin 37). See Figure 3-1 for proper placement. | |||
In multiple supply operation, this pin is not used. | |||
PFBIN1 | 18 | I | Power Feedback Input: These pins are fed with power from PFBOUT (pin 23) in single supply operation. |
PFBIN2 | 37 | In multiple supply operation, connect a 1.55V external power supply to these pins. Connect a small capacitor of 0.1µF close to each pin. To power down the internal linear regulator, write to register 0x00d0. | |
VDD_IO | 32, 48 | P | I/O 3.3V, 2.5V, or 1.8V Supply - For details, see Section 3.2.3 |
IOGND | 35, 47 | P | I/O ground |
DGND | 36 | P | Digital ground |
AVDD33 | 22 | P | Analog 3.3V power supply |
AGND | 15, 19 | P | Analog ground |
RESERVED | 20 | I/O | RESERVED: This pin must be pulled-up through 2.2kΩ resistor to AVDD33 supply. |
This section includes information on the various configuration options available with the TLK111. The configuration options described below include:
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Bootstrap configuration is a convenient way to configure the TLK111 into specific modes of operation. Some of the functional pins are used as configuration inputs. The logic states of these pins are sampled during reset and are used to configure the device into specific modes of operation. The table below describes bootstrap configuration.
A 2.2kΩ resistor is used for pull-down or pull-up to change the default configuration. If the default option is desired, then there is no need for external pull-up or pull down resistors. Because these pins may have alternate functions after reset is deasserted, they must not be connected directly to VCC or GND.
PIN | TYPE | |||||||
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NAME | NO. | DESCRIPTION | ||||||
PHYAD0 (COL) PHYAD1 (RXD_0) PHYAD2 (RXD_1) PHYAD3 (RXD_2) PHYAD4 (RXD_3) |
42 43 44 45 46 |
S, O, PD / PU | PHY Address [4:0]: The TLK111 provides five PHY address pins, the states of which are latched into an internal register at system hardware reset. The TLK111 supports PHY Address values 0 (<00000>) through 31 (<11111>). PHYAD[4:1] pins have weak internal pull-down resistors, and PHYAD[0] has weak internal pull-up resistor, setting the default PHYAD if no external resistors are connected. | |||||
SW_STRAP | 21 | I | Software Strapping Mode: The TLK111 provides a mechanism to extend the number of configuration pins to allow wider system programmability of PHY functions. An external pull-down will cause the device to enter SW Strapping Mode. In this mode the device will wake up after Power-up or Reset in Power-Down mode, this will allow the system processor to access dedicated Strapping Registers and configure modes of operation. An access to SW Strapping Mode Release register must be done to take the device out of power-down mode. See Section 3.8 for more details. An external pull-up resistor should be used to disable Software Strapping Mode. | |||||
AN_EN (LED_ACT) AN_1 (LED_SPEED) AN_0 (LED_LINK) |
26 27 28 |
S, O, PU | AN_EN: A high level on this pin puts the part into advertised Auto-Negotiation mode with the capability set by AN_0 and AN_1 pins. A low level on AN_EN puts the part into Forced Mode with the capability set by AN_0 and AN_1 pins. AN_0, AN_1: These input pins control the forced or advertised operating mode according to the following table. The value on these pins is set by connecting the input pins to GND (0) or VCC (1) through 2.2kΩ resistors. DO NOT connect these pins directly to GND or VCC. The states of these pins are latched into the Basic Mode Control Register and the Auto_Negotiation Advertisement Register during Hardware-Reset. The default is 111 because these pins have internal pull-ups. |
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AN_EN | AN_1 | AN_0 | Forced Mode | |||||
0 | 0 | 0 | 10Base-T, Half-Duplex | |||||
0 | 0 | 1 | 10Base-T, Full-Duplex | |||||
0 | 1 | 0 | 100Base-TX, Half-Duplex | |||||
0 | 1 | 1 | 100Base-TX, Full-Duplex | |||||
AN_EN | AN_1 | AN_0 | Advertised Mode | |||||
1 | 0 | 0 | 10Base-T, Half or Full-Duplex | |||||
1 | 0 | 1 | 100Base-TX, Half or Full-Duplex | |||||
1 | 1 | 0 | 10Base-T, Half-Duplex 100Base-TX, Half-Duplex |
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1 | 1 | 1 | 10Base-T, Half orFull-Duplex 100Base-TX, Half or Full-Duplex |
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LED_CFG (CRS) | 40 | S, O, PU | LED Configuration: This option, along with the LEDCR register bit, selects the mode of operation of the LED pins. Default is Mode 1. All modes are also configurable via register access. See PHY Control Register (PHYCR), Address 0x0019 | |||||
AMDIX_EN (RX_ER) | 41 | S, O, PU | Auto-MDIX Enable: This option sets the Auto-MDIX mode. By default, it enables Auto-MDIX. An external pull-down resistor disables Auto-MDIX mode. | |||||
MII_MODE (RX_DV) | 39 | S, O, PD | MII Mode Select: This option selects the operating mode of the MAC data interface. This pin has a weak internal pull-down, and it defaults to normal MII operation mode. An external pull-up causes the device to operate in RMII mode. |
The TLK111 provides best-in-class flexibility of power supplies.
If a single 3.3V power supply is desired, the TLK111 internal regulator provides the necessary core supply voltages. Ceramic capacitors of 10µf and 0.1µf should be placed close to the PFBOUT (pin 23) which is the output of the internal regulator. The PFBOUT pin should be connected to the PFBIN1 and PFBIN2 on the board. A small capacitor of 0.1µF should be placed close to the PFBIN1 (pin 18) and PFBIN2 (pin 37). To operate in this mode, connect the TLK111 supply pins as shown in Figure 3-1.
When a 1.55V external power rail is available, the TLK111 can be configured as shown in Figure 3-2. PFBOUT (pin 23) is left floating. The 1.55V external supply is connected to PFBIN1 (pin 18) and PFBIN2 (pin 37). Furthermore, to lower the power consumption, the internal regulator should be powered down by writing ‘1’ to bit 15 of the VRCR register (0x00d0h).
When operating with dual supplies, follow these guidelines:
The TLK111 digital IO pins can operate with a variable supply voltage. While the primary applications will use 3.3V, VDD_IO can also operate on 2.5V, and for MII mode only, VDD_IO of 1.8V can be used as well. For more details, see Section 9.6.
The following IO or output pins are in hi-Z state when RESET is active (Low).
Pin Name | Type | Internal PU/PD | Pin Name | Type | Internal PU/PD | |
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TXD_3 | IO | PD | RX_ER | IO | PU | |
TX_EN | IO | PD | COL | IO | PU | |
INT/PWDN | IO | PU | RXD_0 | IO | PD | |
LED_ACT | IO | PU | RXD_1 | IO | PD | |
LED_SPEED | IO | PU | RXD_2 | IO | PD | |
LED_LINK | IO | PU | RXD_3 | IO | PD | |
MDIO | IO | TX_CLK | O | |||
RX_DV | IO | PD | CLK25MHz_OUT | O | ||
CRS | IO | PU | RX_CLK | O |
The TLK111 device auto-negotiates to operate in 10Base-T or 100Base-TX. With Auto-Negotiation enabled, the TLK111 negotiates with the link partner to determine the speed and duplex mode. If the link partner cannot Auto-Negotiate, the TLK111 device enters parallel-detect mode to determine the speed of the link partner. Parallel-detect mode uses fixed half-duplex mode.
The TLK111 supports four different Ethernet protocols (10Mbs Half-Duplex, 10Mbs Full-Duplex, 100Mbs Half-Duplex, and 100Mbs Full-Duplex). Auto-Negotiation selects the highest performance protocol based on the advertised ability of the Link Partner. Control the Auto-Negotiation function within the TLK111 by:
The state of the AN_EN, AN_0 and AN_1 pins determine whether the TLK111 is forced into a specific mode, or if Auto-Negotiation advertises a specific ability (or set of abilities) as given in Table 3-1. These pins allow configuration options to be selected without requiring internal register access. The state of AN_EN, AN_0 and AN_1, upon power-up/reset, determines the state of bits [8:5] of the ANAR register (0x04h).
Internal register access controls the Auto-Negotiation function, as defined by the IEEE 802.3u specification. For further detail regarding Auto-Negotiation, see Clause 28 of the IEEE 802.3u specification.
AN_EN | AN_1 | AN_0 | Forced Mode |
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0 | 0 | 0 | 10Base-T, Half-Duplex |
0 | 0 | 1 | 10Base-T, Full-Duplex |
0 | 1 | 0 | 100Base-TX, Half-Duplex |
0 | 1 | 1 | 100Base-TX, Full-Duplex |
AN_EN | AN_1 | AN_0 | Advertised Mode |
1 | 0 | 0 | 10Base-T, Half or Full-Duplex |
1 | 0 | 1 | 100Base-TX, Half or Full-Duplex |
1 | 1 | 0 | 10Base-T, Half Duplex 100Base-TX, Half Duplex |
1 | 1 | 1 | 10Base-T, Half or Full-Duplex 100Base-TX, Half or Full-Duplex |
The TLK111 device automatically determines whether or not it needs to cross over between pairs, eliminating the requirement for an external crossover cable. If the TLK111 interoperates with a device that implements MDI/MDIX crossover, a random algorithm as described in IEEE 802.3 determines which device performs the crossover.
Auto-MDIX is enabled by default and can be configured via pin strap, SW Strap register SWSCR1 (0x09h), bit 14 or via register PHYCR (0x19h), bit 15.
The crossover can be manually forced through bit 14 of the PHYCR (0x19h) register. Neither Auto-Negotiation nor Auto-MDIX is required to be enabled in forcing crossover of the MDI pairs.
Auto-MDIX can be used in the forced 100Base-TX mode. Because in modern networks all the nodes are 100Base-TX, having the Auto-MDIX working in the forced 100Base-TX mode resolves the link faster without the need for the long Auto-Negotiation period.
The 5 PHY address inputs pins are shared with the RXD[3:0] pins and COL pin as shown in Table 3-2.
PIN Number | PHYAD FUNCTION | RXD FUNCTION |
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42 | PHYAD0 | COL |
43 | PHYAD1 | RXD_0 |
44 | PHYAD2 | RXD_1 |
45 | PHYAD3 | RXD_2 |
46 | PHYAD4 | RXD_3 |
Each TLK111 or port sharing an MDIO bus in a system must have a unique physical address. With 5 address input pins, the TLK111 can support PHY Address values 0 (<00000>) through 31 (<11111>). The address-pin states are latched into an internal register at device power-up and hardware reset. Because all the PHYAD[4:0] pins have weak internal pull-down/up resistors, the default setting for the PHY address is 00001 (0x01h).
See Figure 3-3 for an example of a PHYAD connection to external components. In this example, the PHYAD configuration results in address 00011 (0x03h).
The TLK111 can be put into MII-Isolate mode by writing bit 10 of the BMCR register.
When in the MII-Isolate mode, the TLK111 ignores packet data present at the TXD[3:0], TX_EN inputs, and presents a high impedance on the TX_CLK, RX_CLK, RX_DV, RX_ER, RXD[3:0], COL, and CRS outputs. When in isolate mode, the TLK111 continues to respond to all management transactions.
When in isolate mode, the PMD output pair does not transmit packet data, but continues to source 100Base-TX scrambled idles or 10Base-T normal link pulses. The TLK111 can auto-negotiate or parallel detect on the receive signal at the PMD input pair. A valid link can be established for the receiver even when the TLK111 is in Isolate mode.
The TLK111 provides a mechanism to extend the number of configuration pins to allow wider system programmability of PHY functions.
Connecting an external pull-down to pin 21 causes the device to enter SW Strapping Mode after power-up or a hardware reset event. In this mode the device wakes up after power-up/hardware reset in power down mode. While in power down (in SW strap mode only) the PHY allows the system processor to access the dedicated Strapping Registers and configure modes of operation. Once the dedicated Strapping Registers are programmed, setting the SW Strapping Mode Release register bit (“Configuration done”), bit 15 of register SWSCR1(0x0009), must be done in order to take the device out of power-down mode. An internal reset pulse is generated and the SW Strap Register values are latched into internal registers. Unless a new Power-up/HW reset was applied, the configured SW Strap Register values will function as default values. Generation of Software Reset/Software Restart - bits 15 and 14 of register PHYRCR (0x001F) will not clear the configured SW Strap bit values.
There are 3 Software Strapping control registers: SWSCR1 (0x0009), SWSCR2 (0x000A) and SWSCR3(0x000B) contain the configuration bits used as strapping options or virtual strapping pins during HW Reset or Power-Up.
The TLK111 Software Strap mechanism behavior is shown in Figure 3-4.
Figure 3-5 shows the timing relationship for typical SW Strapping programming.
Connecting an external pull-up resistor to pin 21 disables Software Strapping Mode during power up or HW Reset.
The TLK111 supports three configurable Light Emitting Diode (LED) pins. The device supports three LED configurations: Link, Speed, and Activity. Functions are multiplexed among the LEDs into three modes. The LEDs can be controlled by configuration pin and-or internal register bits. Bits 6:5 of the PHY Control register (PHYCR) selects the LED mode as described in Table 3-3.
Mode | LED_CFG[1] (bit 6) |
LED_CFG[0] (bit 5) or (pin 40) |
LED_LINK | LED_SPEED | LED_ACT |
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1 | don't care | 1 | ON for Good Link OFF for No Link |
ON in 100Mbs OFF in 10Mbs |
ON Pulse for Activity OFF for No Activity |
2 | 0 | 0 | ON for Good Link BLINK for Activity |
ON in 100Mbs OFF in 10Mbs |
ON for Collision OFF for No Collision |
3 | 1 | 0 | ON for Good Link BLINK for Activity |
ON in 100Mbs OFF in 10Mbs |
ON for Full Duplex OFF for Half Duplex |
The LED_LINK pin in Mode 1 indicates the link status of the port. The LED is OFF when no link is present. In Mode 2 and Mode 3 it is ON to indicate that the link is good; BLINK indicates that activity is present on either transmit or receive channel. Bits 10:9 of the LEDCR register (0x18) control the blink rate. The default blink rate is 5Hz.
The LED_SPEED pin indicates the data rate of the port, 10Mbs or 100Mbs. This LED is ON when the device is operating in 100Mbs operation. The functionality of this LED is independent of mode selected.
The LED_ACT pin in Mode 1 indicates the presence of either transmit or receive activity. The LED is ON (Pulse) for Activity and OFF for No Activity. In mode 2 this pin indicates the collision status of the port. The LED is ON when there is a collision and OFF when there is no collision. In mode 3 this pin indicates the Duplex status of operation. The LED is ON for Full Duplex and OFF for Half Duplex.
Bits 8:6 of the LEDCR register define the polarity of the signals on the LED pins.
Because the Auto-Negotiation (AN) configuration options share the LED output pins, the external components required for configuration-pin programming and those for LED usage must be considered in order to avoid contention.
See Figure 3-6 for an example of AN_0, AN_1, AN_EN connections to external components. In this example, the configuration results in Auto-Negotiation with 10/100 Full-Duplex advertised.
In addition, the TLK111 supports by register access a multi-configurable LED (MLED). The MLED by default is not activated; by register access it can be routed through either the 3 LED pins 26-28 or the COL pin, allowing support of 4 LEDS. When MLED is routed to the COL pin, the COL functionality is disabled. REG 0x0025 (MLEDCR Register) controls the MLED routing and configurations. The different MLED modes are configured by bits [6:3] as described in Table 3-4.
(bit 6:3) |
Mode | (bit 6:3) | Mode | |
---|---|---|---|---|
0x0 | Link OK | 0x6 | LED Speed: High for 10 Base TX | |
0x1 | RX/TX Activity | 0x7 | Full Duplex | |
0x2 | TX Activity | 0x8 | Link OK / Blink on TX/RX Activity | |
0x3 | RX Activity | 0x9 | Active stretch signal | |
0x4 | Collision | 0xA | MI_LINK (100BT+FD) | |
0x5 | LED Speed: High for 100 Base TX |
The TLK111 provides several options for Loopback that test and verify various functional blocks within the PHY. Enabling loopback mode allows in-circuit testing of the TLK111 digital and analog data path. Generally, the TLK111 may be configured to one of the Near-end loopback modes or to the Far-end (reverse) loopback.
Near-end loopback provides the ability to loop the transmitted data back to the receiver via the digital or analog circuitry. The point at which the signal is looped back is selected using loopback control bits with several options being provided. Figure 3-7 shows the PHY near-end loopback functionality.
The Near-end Loopback mode is selected by setting the respective bit in the BIST Control Register (BISCR), MII register address 0x0016. MII loopback can be selected by using the BMCR register at address 0x0000, bit [14].
The Near-end Loopback can be selected according to the following:
Table 3-5 describes the available operational modes for each loop mode:
Loop Mode | MII | PCS Input | PCS Output | Digital | Analog(1) | External |
---|---|---|---|---|---|---|
Operational Setting | Force/ANEG 100/10 | Force 100/10 | Force 100 | Force 100 | Force 10/100 ANEG 10 | Force/ANEG 100/10 |
Operational MAC int. | MII Only | MII or RMII | MII or RMII | MII or RMII | MII or RMII | MII or RMII |
While in MII Loopback mode, there is no link indication, but packets propagate back to the MAC. While in MII Loopback mode the data is looped back, and can also be transmitted onto the media. For transmitting data during MII loopback in 100BT only please use bit [6] in the BISCR Register address 0x0016. For proper operation in Analog Loopback mode, attach 100Ω terminations to the RJ45 connector. External Loopback can be performed while working in normal mode (Bits 3:0 of the BISCR register are asserted to 0, and on the RJ45 connector, pin 1 is connected to pin 3 and pin 2 is connected to pin 6). To maintain the desired operating mode, Auto-Negotiation should be disabled before selecting Loopback mode. This constraint does not apply for external-loopback mode. For selected loopback Delay propagation timing please see Section 9.9.21.
Far-end (Reverse) loopback is a special test mode to allow testing the PHY from the link-partner side. In this mode, data that is received from the link partner passes through the PHY's receiver, looped back on the MII and transmitted back to the link partner. Figure 3-8 shows Far-end loopback functionality.
The Reverse Loopback mode is selected by setting bit 4 in the BIST Control Register (BISCR), MII register address 0x0016.
While in Reverse Loopback mode the data is looped back and also transmitted onto the MAC Interface and all data signals that come from the MAC are ignored.
Table 3-6 describes the operating modes for Far-End Loopback.
Operational MAC Int. | MII Mode | RMII Mode |
---|---|---|
Operational Setting | Force/ANEG 10/100 | Force/ANEG 10 |
The device incorporates an internal PRBS Built-in Self Test (BIST) circuit to accommodate in-circuit testing or diagnostics. The BIST circuit can be used to test the integrity of the transmit and receive data paths. The BIST can be performed using both internal loopback (digital or analog) or external loopback using a cable fixture. The BIST simulates pseudo-random data transfer scenarios in format of real packets and Inter-Packet Gap (IPG) on the lines. The BIST allows full control of the packet lengths and of the IPG.
The BIST is implemented with independent transmit and receive paths, with the transmit block generating a continuous stream of a pseudo-random sequence. The device generates a 15-bit pseudo-random sequence for the BIST. The received data is compared to the generated pseudo-random data by the BIST Linear Feedback Shift Register (LFSR) to determine the BIST pass/fail status. The number of error bytes that the PRBS checker received is stored in the BICSR1 register (0x001Bh). The status of whether the PRBS checker is locked to the incoming receive bit stream, whether the PRBS has lost sync, and whether the packet generator is busy, can be read from the BISCR register (0x0016h). While the lock and sync indications are required to identify the beginning of proper data reception, for any link failures or data corruption, the best indication is the contents of the the error counter in the BICSR1 register (0x001Bh).
The PRBS test can be put in a continuous mode or single mode by using bit 14 of the BISCR register (0x0016h). In continuous mode, when one of the PRBS counters reaches the maximum value, the counter starts counting from zero again. In single mode, when the PRBS counter reaches its maximum value, the PRBS checker stops counting.
The device allows the user to control the length of the PRBS packet. By programming the BICSR2 register (0x001Ch) one can set the length of the PRBS packet. There is also an option to generate a single-packet transmission of two types, 64 and 1518 bytes, through register bit 13 of the BISCR register (0x0016h). The single generated packet is composed of a constant data.
With the vast deployment of Ethernet devices, the need for reliable, comprehensive and user-friendly cable diagnostic tool is more important than ever. The wide variety of cables, topologies, and connectors deployed results in the need to non-intrusively identify and report cable faults. The TI cable-diagnostic unit provides extensive information about cable integrity.
The TLK111 offers the following capabilities in its Cable Diagnostic tools kit:
The TLK111 uses Time Domain Reflectometry (TDR) to determine the quality of the cables, connectors, and terminations in addition to estimating the cable length. Some of the possible problems that can be diagnosed include opens, shorts, cable impedance mismatch, bad connectors, termination mismatches, cross faults, cross shorts and any other discontinuities along the cable.
The TLK111 transmits a test pulse of known amplitude (1V or 2.5V) down each of the two pairs of an attached cable. The transmitted signal continues down the cable and reflects from each cable imperfection, fault, bad connector, and from the end of the cable itself. After the pulse transmission the TLK111 measures the return time and amplitude of all these reflected pulses. This technique enables measuring the distance and magnitude (impedance) of non-terminated cables (open or short), discontinuities (bad connectors), and improperly-terminated cables with ±1m accuracy.
The TLK111 also uses data averaging to reduce noise and improve accuracy. The TLK111 can record up to five reflections within the tested pair. If more than 5 reflections are recorded, the TLK111 saves the first 5 of them. If a cross fault is detected, the TDR saves the first location of the cross fault and up to 4 reflections in the tested channel. The TLK111 TDR can measure cables up to 200m in length.
For all TDR measurements, the transformation between time of arrival and physical distance is done by the external host using minor computations (such as multiplication, addition and lookup tables). The host must know the expected propagation delay of the cable, which depends, among other things, on the cable category (for example, CAT5, CAT5e, or CAT6).
TDR measurement is allowed in the TLK111 in the following scenarios:
The TLK111 also supports Active Link Cable Diagnostic (ALCD). The ALCD offers a passive method to estimate the cable length during active link. The ALCD uses passive digital signal processing based on adapted data, thus enabling measurement of cable length with an active link partner.
The ALCD Cable length measurement accuracy is ±5m for the pair used in the Rx path (due to the passive nature of the test, only the receive path is measured).
The Media Independent Interface (MII) is a synchronous 4-bit wide nibble data interface that connects the PHY to the MAC in 100B-TX and 10B-T modes. The MII is fully compliant with IEEE802.3-2002 clause 22.
The MII signals are summarized below.
Data signals | TXD [3:0] | ||
RXD [3:0] | |||
Transmit and receive-valid signals | TX_EN | ||
RX_DV | |||
Line-status signals | CRS (carrier sense) | ||
COL (collision) |
Figure 4-1 shows the MII-mode signals.
The Isolate bit (BMCR register bit 10), defined in IEEE802.3-2002, electrically isolates the PHY from the MII (if set, all transactions on the MII interface are ignored by the PHY).
Additionally, the MII interface includes the carrier sense signal CRS, as well as a collision detect signal COL. The CRS signal asserts to indicate the reception of data from the network or as a function of transmit data in Half Duplex mode. The COL signal asserts as an indication of a collision which can occur during half-duplex operation when both transmit and receive operation occur simultaneously.
TLK111 incorporates the Reduced Media Independent Interface (RMII) as specified in the RMII specification (rev1.2) from the RMII consortium. The purpose of this interface is to provide a low cost alternative to the IEEE 802.3u MII as specified in Clause 22. Architecturally, the RMII specification provides an additional reconciliation layer on either side of the MII, but can be implemented in the absence of an MII.
The RMII specification has the following characteristics:
In this mode, data transfers two bits at a time using the 50MHz RMII reference clock for both transmit and receive. RMII mode uses the following pins:
Signal | Pin |
XI (RMII reference clock is 50MHz) | 34 |
TXD_0 | 3 |
TXD_1 | 4 |
TX_EN | 2 |
CRS_DV | 40 |
RX_ER | 41 |
RXD_0 | 43 |
RXD_1 | 44 |
Data on TXD [1:0] are latched at the PHY with reference to the reference-clock edges on the XI pin. Data on RXD [1:0] are latched at the MAC with reference to the same reference clock edges on the XI pin. The RMII operates at the same speed (50MHz) in both 10B-T and 100B-TX. In 10B-T the data is 10 times slower than the reference clock, so transmit data is sampled every 10 clocks. Likewise, receive data is generated on every 10th clock so that an attached MAC device can sample the data every 10 clocks.
In addition, RMII mode supplies an RX_DV signal which allows a simpler method of recovering receive data without the need to separate RX_DV from the CRS_DV indication. RX_ER is also supported even though not required by RMII spec (The TLK111 supports optional use of RX_ER and RX_DV in RMII as an extra feature). RMII mode requires a 50MHz oscillator connected to the device XI pin.
The TLK111 supports a special mode called “RMII receive clock” mode. This mode, which is not part of the RMII specification, allows synchronization of the MAC-PHY RX interface. In this mode, the PHY generates a recovered 50MHz clock through the RX_CLK pin and synchronizes the RXD[1:0], CRS_DV, RX_DV and RX_ER signals to this clock. Setting register 0x000A bit [0] is required to activate this mode.
Figure 4-2 describes the RMII signals connectivity between the TLK111 and any MAC device.
RMII function includes a programmable elastic buffer to adjust for the frequency differences between the reference clock and the recovered receive clock. The programmable elastic buffer minimizes internal propagation delay based on expected maximum packet size and clock accuracy.
Table 4-1 indicates how to program the buffer FIFO based on the expected max packet size and clock accuracy. It assumes that the RMII reference clock and the far-end transmitter clock have the same accuracy.
Start Threshold RBR[1:0] | Latency Tolerance | Recommended packet size at ±50ppm | Recommended packet size at ±100ppm |
---|---|---|---|
1(4-bits) | 2 bits | 2400 bytes | 1200 bytes |
2(8-bits) | 6 bits | 7200 bytes | 3600 bytes |
3(12-bits) | 10 bits | 12000 bytes | 6000 bytes |
0(16-bits) | 14 bits | 16800 bytes | 8400 bytes |
The Serial Management Interface (SMI), provides access to the TLK111 internal register space for status information and configuration. The SMI is compatible with IEEE802.3-2002 clause 22. The implemented register set consists of all the registers required by the IEEE802.3-2002, plus several others to provide additional visibility and controllability of the TLK111 device.
The SMI includes the MDC management clock input and the management MDIO data pin. The MDC clock is sourced by the external management entity, also called Station (STA), and can run at a maximum clock rate of 25MHz. MDC is not expected to be continuous, and can be turned off by the external management entity when the bus is idle.
The MDIO is sourced by the external management entity and by the PHY. The data on the MDIO pin is latched on the rising edge of the MDC clock. The MDIO pin requires a pull-up resistor (2.2kΩ) which, during IDLE and turnaround, pulls MDIO high.
Up to 32 PHYs can share a common SMI bus. To distinguish between the PHYs, a 5-bit address is used. During power-up reset, the TLK111 latches the PHYAD[4:0] configuration pins (Pin 42 to Pin 46) to determine its address.
The management entity must not start an SMI transaction in the first cycle after power-up reset. To maintain valid operation, the SMI bus must remain inactive at least one MDC cycle after hard reset is de-asserted.
In normal MDIO transactions, the register address is taken directly from the management-frame reg_addr field, thus allowing direct access to 32 16-bit registers (including those defined in IEEE802.3 and vendor specific). The data field is used for both reading and writing. The Start code is indicated by a <01> pattern. This pattern makes sure that the MDIO line transitions from the default idle line state. Turnaround is defined as an idle bit time inserted between the Register Address field and the Data field. To avoid contention during a read transaction, no device may actively drive the MDIO signal during the first bit of Turnaround. The addressed TLK111 drives the MDIO with a zero for the second bit of turnaround and follows this with the required data. Figure 4-3 shows the timing relationship between MDC and the MDIO as driven/received by the Station (STA) and the TLK111 (PHY) for a typical register read access.
For write transactions, the station-management entity writes data to the addressed TLK111, thus eliminating the requirement for MDIO Turnaround. The Turnaround time is filled by the management entity by inserting <10>. Figure 4-4 shows the timing relationship for a typical MII register write access. The frame structure and general read/write transactions are shown in Table 4-2, Figure 4-3, and Figure 4-4.
MII Management Serial Protocol | <idle><start><op code><device addr><reg addr><turnaround><data><idle> |
---|---|
Read Operation | <idle><01><10><AAAAA><RRRRR><Z0><xxxx xxxx xxxx xxxx><idle> |
Write Operation | <idle><01><01><AAAAA><RRRRR><10><xxxx xxxx xxxx xxxx><idle> |
The TLK111 SMI function supports read/write access to the extended register set using registers REGCR(0x000Dh) and ADDAR(0x000Eh) and the MDIO Manageable Device (MMD) indirect method defined in IEEE802.3ah Draft for clause 22 for accessing the clause 45 extended register set.
The standard register set, MDIO registers 0 to 31, is accessed using the normal direct-MDIO access or the indirect method, except for register REGCR(0x000Dh) and ADDAR(0x000Eh) which is accessed only using the normal MDIO transaction. The SMI function will ignore indirect accesses to these registers.
REGCR(0x000Dh) is the MDIO Manageable MMD access control. In general, register REGCR(4:0) is the device address DEVAD that directs any accesses of ADDAR(0x000Eh) register to the appropriate MMD. Specifically, the TLK111 uses the vendor-specific DEVAD[4:0] = "11111" for accesses. All accesses through registers REGCR and ADDAR must use this DEVAD. Transactions with other DEVAD are ignored. REGCR[15:14] holds the access function: address (00), data with no post increment (01), data with post increment on read and writes (10) and data with post increment on writes only (11).
The following sections describe how to perform operations on the extended register set using register REGCR and ADDAR.
To set the address register:
Subsequent writes to register ADDAR (step 2) continue to write the address register.
To read the address register:
Subsequent reads to register ADDAR (step 2) continue to read the address register.
To write a register in the extended register set:
Subsequent writes to register ADDAR (step 4) continue to rewrite the register selected by the value in the address register.
Note: steps (1) and (2) can be skipped if the address register was previously configured.
To read a register in the extended register set:
Subsequent reads from register ADDAR (step 4) continue reading the register selected by the value in the address register.
Note: steps (1) and (2) can be skipped if the address register was previously configured.
Subsequent writes to register ADDAR (step 4) write the next higher addressed data register selected by the value of the address register; the address register is incremented after each access.
To read a register in the extended register set and automatically increment the address register to the next higher value following the write operation:
Subsequent reads to register ADDAR (step 4) read the next higher addressed data register selected by the value of the address register; the address register is incremented after each access.
The TLK111 Fast Ethernet transceiver is a physical layer core for Ethernet 100Base-TX and 10Base-T applications. The TLK111 contains all the active circuitry required to implement the physical layer functions to transmit and receive data on standard CAT 3 and 5 unshielded twisted pair. The core supports the IEEE 802.3 Standard Fast Media Independent Interface (MII), as well as the Reduced Media Independent Interface (RMII), for direct connection to a MAC/Switch port.
The TLK111 uses mixed signal processing to perform equalization, data recovery and error correction to achieve robust and low power operation over the existing CAT 5 twisted pair wiring. The TLK111 architecture not only meets the requirements of IEEE802.3, but maintains a high level of margin over the IEEE requirements for NEXT, Alien and External noise.
In 100Base-TX, the MAC feeds the 100Mbps transmit data in 4-bit wide nibbles through the MII interface. The data is encoded into 5-bit code groups, encapsulated with control code symbols and serialized. The control-code symbols indicate the start and end of the frame and code other information such as transmit errors. When no data is available from the MAC, IDLE symbols are constantly transmitted. The serialized bit stream is fed into a scrambler. The scrambled data stream passes through an NRZI encoder and then through an MLT3 encoder. Finally, it is fed to the DAC and transmitted through one of the twisted pairs of the cable.
According to IEEE 802.3:
“If TX_EN is de-asserted on an odd nibble boundary, PHY should extend TX_EN by one TX_CLK cycle and behave as if TX_ER were asserted during that cycle”.
The TLK111 supports Error Forwarding in MII transmission from the MAC to the PHY. Error forwarding allows adding information to the frame to be used as an error code between the 2 MACs. The error code informs the receiving MAC on the link partner side of the reason for the error from the transmitting side. If the MAC transmits an odd number of nibbles, an additional error nibble is added to the transmitted frame just before the end of the transmission.To turn off Transmit Error Forwarding, write to bit 1 of register SWSCR2 (0x000A). If Error Forwarding is disabled, delivered packets contain either odd or even numbers of nibbles.
In Figure 5-2, Error Code Forwarding functionality is illustrated. The wave diagram demonstrates MAC’s transmitted signals in one side and MAC’s reception signals on link partner side.
The transmit data that is received from the MAC first passes through the 4-Bit to 5-Bit encoder. This block encodes 4-bit nibble into 5-bit code-groups according to the Table 5-1. Each 4-bit data nibble is mapped to 16 of the 32 possible code-groups. The remaining 16 code-groups are either used for control information or they are considered as not valid.
The code-group encoder substitutes the first 8-bits of the MAC preamble with a J/K code-group pair (11000 10001) upon transmission. The code-group encoder continues to replace subsequent 4-bit preamble and data nibbles with corresponding 5-bit code-groups. At the end of the transmit packet, upon the de-assertion of Transmit Enable signal from the MAC, the code-group encoder adds the T/R code-group pair (01101 00111) indicating the end of the frame.
After the T/R code-group pair, the code-group encoder continuously adds IDLEs into the transmit data stream until the next transmit packet is detected.
4-Bit Code | Symbol | 5-Bit Code | Receiver Interpretation |
---|---|---|---|
0000 | 0 | 11110 | Data |
0001 | 1 | 01001 | |
0010 | 2 | 10100 | |
0011 | 3 | 10101 | |
0100 | 4 | 01010 | |
0101 | 5 | 01011 | |
0110 | 6 | 01110 | |
0111 | 7 | 01111 | |
1000 | 8 | 10010 | |
1001 | 9 | 10011 | |
1010 | A | 10110 | |
1011 | B | 10111 | |
1100 | C | 11010 | |
1101 | D | 11011 | |
1110 | E | 11100 | |
1111 | F | 11101 | |
IDLE AND CONTROL CODES | |||
DESCRIPTION | Symbol(1) | 5-Bit Code | |
Inter-Packet IDLE | I | 11111 | IDLE |
First nibble of SSD | J | 11000 | First nibble of SSD, translated to "0101" following /I/ (IDLE), else RX_ER asserted high |
Second nibble of SSD | K | 10001 | Second nibble of SSD, translated to "0101" following /J/, else RX_ER asserted high |
First nibble of ESD | T | 01101 | First nibble of ESD, causes de-assertion of CRS if followed by /R/, else assertion of RX_ER |
Second nibble of ESD | R | 00111 | Second nibble of ESD, causes de-assertion of CRS if following /T/, else assertion of RX_ER |
Transmit Error Symbol | H | 00100 | RX_ER |
Invalid Symbol | V | 00000 | INVALID
RX_ER asserted high If during RX_DV |
V | 00001 | ||
V | 00010 | ||
V | 00011 | ||
V | 00101 | ||
V | 00110 | ||
V | 01000 | ||
V | 01100 |
The purpose of the scrambler is to flatten the power spectrum of the transmitted signal, thus reduce EMI. The scrambler seed is generated with reference to the PHY address so that multiple PHYs that reside within the system will not use the same scrambler sequence.
To comply with the TP-PMD standard for 100Base-TX transmission over CAT-5 unshielded twisted pair cable, the scrambled data must be NRZI encoded. The serial binary data stream output from the NRZI encoder is further encoded to MLT-3. MLT-3 is a tri-level code where a change in the logic level represents a code bit '1' and the logic output remaining at the same level represents a code bit '0'.
The multipurpose programmable transmit Digital to Analog Converter (DAC) receives digital coded symbols and generates filtered analog symbols to be transmitted on the line. In 100B-TX the DAC applies a low-pass shaping filter to minimize EMI. The DAC is designed to improve the return loss requirements and enable the use of low-cost transformers.
Digital pulse-shape filtering is also applied in order to conform to the pulse masks defined by standard and to reduce EMI and high frequency signal harmonics.
In 100B-TX, the ADC sampled data is passed to an adaptive equalizer. The adaptive equalizer drives the received symbols to the MLT3 decoder. The decoded NRZ symbols are transferred to the descrambler block for descrambling and deserialization.
The Receiver Analog Front End (AFE) resides in front of the 100B-TX receiver. The AFE consists of an Analog to Digital Converter (ADC), receive filters and a Programmable Gain Amplifier (PGA).
The ADC samples the input signal at the 125MHz clock recovered by the timing loop and feeds the data into the adaptive equalizer. The ADC is designed to optimize the SNR performance at the receiver input while maintaining high power-supply rejection ratio and low power consumption. There is only one ADC in the TLK111, which receives the analog input data from the relevant cable pair, according to MDI-MDIX resolution.
The PGA, digitally controlled by the adaptive equalizer, fully uses the dynamic range of the ADC by adjusting the incoming-signal amplitude. Generally, the PGA attenuates short-cable strong signals and amplifies long-cable weak signals.
The adaptive equalizer removes Inter-Symbol Interference (ISI) from the received signal introduced by the channel and analog Tx/Rx filters. The TLK111 includes both Feed Forward Equalization (FFE) and Decision Feedback Equalization (DFE). The combination of both adaptive modules with the adaptive gain control results in a powerful equalizer that can eliminate ISI and compensate for cable attenuation for longer-reach cables. In addition, the Equalizer includes a Shift Gear Step mechanism to provide fast convergence on the one hand and small residual-adaptive noise in steady state on the other hand.
The DC offset of the transmitted signal is shifted down or up based on the polarity of the transmitted data because the MLT-3 data is coupled onto the CAT 5 cable through a transformer that is high-pass in nature. This phenomenon is called Baseline wander. To prevent corruption of the received data because of this phenomenon, the receiver corrects the baseline wander and can receive the ANSI TP-PMD-defined "killer packet" with no bit errors.
The TLK111 decodes the MLT-3 information from the Digital Adaptive Equalizer block to binary NRZI data. The NRZI-to-NRZ decoder is used to present NRZ-formatted data to the descrambler.
The descrambler is used to descramble the received NRZ data. The data is further deserialized and the parallelized data is aligned to 5-bit code-groups and mapped into 4-bit nibbles. At initialization, the 100B-TX descrambler uses the IDLE-symbols sequence to lock on the far-end scrambler state. During that time, neither data transmission nor reception is enabled. After the far-end scrambler state is recovered, the descrambler constantly monitors the data and checks whether it still synchronized. If, for any reason, synchronization is lost, the descrambler tries to re-acquire synchronization using the IDLE symbols.
The code-group decoder functions as a look up table that translates incoming 5-bit code-groups into 4-bit nibbles. The code-group decoder first detects the Start of Stream Delimiter (SSD) /J/K/ code-group pair preceded by IDLE code-groups at the start of a packet. Once the code group alignment is determined, it is stored and used until the next start-of-frame. The decoder replaces the /J/K/ with the MAC preamble. Specifically, the /J/K/ 10-bit code-group pair is replaced by the nibble pair (0101 0101). All subsequent 5-bit code-groups are converted to the corresponding 4-bit nibbles for the duration of the entire packet. This conversion ceases upon the detection of the /T/R/ code-group pair denoting the End-of-Stream Delimiter (ESD) or with the reception of a minimum of two IDLE code-groups.
The receiver must lock on the far-end transmitter clock in order to sample the data at the optimum timing. The timing loop recovers the far-end clock frequency and offset from the received data samples and tracks instantaneous phase drifts caused by timing jitter.
The TLK111 has a robust adaptive-timing loop (Tloop) mechanism that is responsible for tracking the Far-End TX clock and adjusting the AFE sampling point to the incoming signal. The Tloop implements an advanced tracking mechanism that when combined with different available phases, always keeps track of the optimized sampling point for the data, and thus offers a robust RX path,tolerant to both PPM and Jitter. The TLK111 is capable of dealing with PPM and jitter at levels far higher than those defined by the standard.
In 10B-T the digital phase lock loop (DPLL) function recovers the far-end link-partner clock from the received Manchester signal. The DPLL is able to combat clock jitter of up to ±18ns and frequency drifts of ±500ppm between the local PHY clock and the far-end clock. The DPLL feeds the decoder with a decoded serial bit stream.
The integrated analog Phase-Locked Loop (PLL) provides the clocks to the analog and digital sections of the PHY. The PLL is driven by an external reference clock (sourced at the XI,XO pins with a crystal oscillator, or at XI with an external reference clock).
The TLK111 implements the link monitor State Machine (SM) as defined by the IEEE 802.3 100Base-TX Standard. In addition, the TLK111 enables several add-ons to the link monitor SM activated by configuration bits. The new add-ons include the recovery state which enables the PHY to attempt recovery in the event of a temporary energy-loss situation before entering the LINK_FAIL state, thus restarting the whole link establishment procedure. This sequence allows significant reduction of the recovery time in scenarios where the link loss is temporal.
In addition, the link monitor SM enables moving to the LINK_DOWN state based on descrambler synchronization failure and not only on Signal_Status indication, which shortens the drop-link down time. These add-ons are supplementary to the IEEE standard and are bypassed by default.
The signal detect function of the TLK111 is incorporated to meet the specifications mandated by the ANSIFDDI TP-PMD Standard as well as the IEEE 802.3 100Base-TX Standard for both voltage thresholds and timing parameters.
The energy-detector module provides signal-strength indication in various scenarios. Because it is based on an IIR filter, this robust energy detector has excellent reaction time and reliability. The filter output is compared to predefined thresholds in order to decide the presence or absence of an incoming signal.
The energy detector also implements hysteresis to avoid jittering in signal-detect indication. In addition it has fully-programmable thresholds and listening-time periods, enabling shortening of the reaction time if required.
A Bad Start of Stream Delimiter (Bad SSD) is any transition from consecutive idle code-groups to non-idle code-groups which is not prefixed by the code-group pair /J/K. If this condition is detected, the TLK111 asserts RX_ER, and presents RXD[3:0] = 1110 to the MII for the cycles that correspond to received 5B code-groups until at least two IDLE code groups are detected. In addition, the FCSCR register (0x14h) is incremented by one for every error in the nibble.
When at least two IDLE code groups are detected, RX_ER and CRS are de-asserted.
In 10B-T, after the far-end clock is recovered, the received Manchester symbols pass to the Manchester decoder. The serial decoded bit stream is aligned to the start of the frame, de-serialized to 4-bit wide nibbles and sent to the MAC through the MII.
The squelch feature determines when valid data is present on the differential receive inputs. The TLK111 implements a squelch to prevent impulse noise on the receive inputs from being mistaken for a valid signal. Squelch operation is independent of the 10Base-T operating mode. The squelch circuitry employs a combination of amplitude and timing measurements (as specified in the IEEE 802.3 10Base-T standard) to determine the validity of data on the twisted-pair inputs.
The signal at the start of a packet is checked by the squelch, and any pulses not exceeding the squelch level (either positive or negative, depending upon polarity) are rejected. When this first squelch level is exceeded correctly, the opposite squelch level must then be exceeded no earlier than 50ns. Finally, the signal must again exceed the original squelch level no earlier than 50ns to qualify as a valid input waveform, and not be rejected. This checking procedure results in the typical loss of three preamble bits at the beginning of each packet. When the transmitter is operating, five consecutive transitions are checked before indicating that valid data is present. At this time, the squelch circuitry is reset.
When in Half-Duplex mode, a 10Base-T collision is detected when receive and transmit channels are active simultaneously. Collisions are reported by the COL signal on the MII.
The COL signal remains set for the duration of the collision. If the PHY is receiving when a collision is detected, it is reported immediately (through the COL pin).
Carrier Sense (CRS) may be asserted due to receive activity after valid data is detected via the squelch function. For 10Mb/s Half Duplex operation, CRS is asserted during either packet transmission or reception. For 10Mb/s Full Duplex operation, CRS is asserted only during receive activity.
CRS is de-asserted following an end-of-packet.
Jabber is a condition in which a station transmits for a period of time longer than the maximum permissible packet length, usually due to a fault condition. The jabber function monitors the TLK111 output and disables the transmitter if it attempts to transmit a packet of longer than legal size. A jabber timer monitors the transmitter and disables the transmission if the transmitter is active for approximately 100ms.
When disabled by the Jabber function, the transmitter stays disabled for the entire time that the ENDEC module's internal transmit enable is asserted. This signal must be de-asserted for approximately 500ms (the unjab time) before the Jabber function re-enables the transmit outputs.
The Jabber function is only available and active in 10Base-T mode.
Swapping the wires within the twisted pair causes polarity errors. Wrong polarity affects the 10B-T PHYs. The 100B-TX is immune to polarity problems because it uses MLT3 encoding. The 10B-T automatically detects reversed polarity according to the received link pulses or data.
External 10Base-T filters are not required when using the TLK111, because the required signal conditioning is integrated into the device. Only isolation transformers and impedance matching resistors are required for the 10Base-T transmit and receive interface. The internal transmit filtering ensures that all the harmonics in the transmit signal are attenuated by at least 30dB.
The TLK111 has two basic 10Base-T operational modes:
The auto-negotiation function, described in detail in IEEE802.3 chapter 28, provides the means to exchange information between two devices and automatically configure both of them to take maximum advantage of their abilities.
Auto negotiation uses the 10B-T link pulses to encapsulate the transmitted data in a sequence of pulses, also referred to as a Fast Link Pulses (FLP) burst. The FLP Burst consists of a series of closely spaced 10B-T link integrity test pulses that form an alternating clock/data sequence. Extraction of the data bits from the FLP Burst yields a Link Code Word that identifies the operational modes supported by the remote device, as well as some information used for the auto negotiation function’s handshake mechanism.
The information exchanged between the devices during the auto-negotiation process consists of the devices' abilities such as duplex support and speed. This information allows higher levels of the network (MAC) to send to the other link partner vendor-specific data (via the Next Page mechanism, see below), and provides the mechanism for both parties to agree on the highest performance mode of operation.
When auto negotiation has started, the TLK111 transmits FLP on one twisted pair and listens on the other, thus trying to find out whether the other link partner supports the auto negotiation function as well. The decision on what pair to transmit/listen depends on the MDI/MDI-X state. If the other link partner activates auto negotiation, then the two parties begin to exchange their information. If the other link partner is a legacy PHY or does not activate the auto negotiation, then the TLK111 uses the parallel detection function, as described in IEEE802.3 chapters 40 and 28, to determine 10B-T or 100B-TX operation modes.
The TLK111 initiates the auto negotiation function if it is enabled through the configuration jumper options AN_EN, AN_1 and AN_0 (pins 34,35,36) and one of the following events have happened:
The auto-negotiation function is also initiated when the auto-negotiation enable bit is set in register BMCR (0x0000h) bit 12 and one of the following events has happened:
To disable the auto-negotiation function during operation, clear register BMCR (0x0000h) bit 12. During operation, setting/resetting this register does not affect the TLK111 operation. For the changes to take place, issue a restart command through register BMCR (0x0000h) bit 9.
The auto-negotiation options can be configured through the configuration bits AN_EN, AN_1 and AN_0 as described in Table 5-2. The configuration bits allow the user to disable/enable the auto negotiation, and select the desirable advertisement features.
During hardware/software reset, the values of these configuration bits are latched into the auto-negotiation registers and available for user read and modification.
AN_EN | AN_1 | AN_0 | Forced Mode |
---|---|---|---|
0 | 0 | 0 | 10Base-T, Half-Duplex |
0 | 0 | 1 | 10Base-T, Full-Duplex |
0 | 1 | 0 | 100Base-TX, Half-Duplex |
0 | 1 | 1 | 100Base-TX, Full-Duplex |
AN_EN | AN_1 | AN_0 | Advertised Mode |
1 | 0 | 0 | 10Base-T, Half or Full-Duplex |
1 | 0 | 1 | 100Base-TX, Half or Full-Duplex |
1 | 1 | 0 | 10Base-T,Half-Duplex 100Base-TX, Half-Duplex |
1 | 1 | 1 | 10Base-T,Half or Full-Duplex 100Base-TX, Half or Full-Duplex |
The TLK111 supports the optional feature of the transmission and reception of auto-negotiation additional (vendor specific) next pages.
If next pages are needed, the user must set register ANAR(0x0004h) bit 15 to '1'. The next pages are then sent and received through registers ANNPTR(0x0007h) and ANLNPTR(0x0008h), respectively. The user must poll register ANER(0x0006h) bit 1 to check whether a new page has been received, and then read register ANLNPTR for the received next page's content. Only after register ANLNPTR is read may the user write to register ANNPTR the next page to be transmitted. After register ANNPTR is written, new next pages overwrite the contents of register ANLNPTR.
If register ANAR(0x0004h) bit 15 is set, then the next page sequence is controlled by the user, meaning that the auto-negotiation function always waits for register ANNPTR to be written before transmitting the next page.
If additional user-defined next pages are transmitted and the link partner has more next pages to send, it is the user's responsibility to keep writing null pages (of value 0x2001) to register ANNPTR until the link partner notifies that it has sent its last page (by setting bit 15 of its transmitted next page to zero).
The TLK111 includes advanced link-down capabilities that support various real-time applications. The link-down mechanism of the TLK111 is configurable and includes enhanced modes that allow extremely fast reaction times to link-drops.
As described in Figure 5-3, the TLK111 link loss mechanism is based on a time window search period, in which the signal behavior is monitored. The T1 window is set by default to reduce typical link-drops to less than 1ms.
The TLK111 supports enhanced modes that shorten the window called Fast Link Down mode. In this mode, which can be configured in Software Strap Control Register 3 (SWSCR3), address 0x000B, bits 3:0, the T1 window is shortened significantly, in most cases less than 10µs. In this period of time there are several criteria allowed to generate link loss event and drop the link:
The Fast Link Down functionality allows the use of each of these options separately or in any combination. Note that since this mode enables extremely quick reaction time, it is more exposed to temporary bad link-quality scenarios.
The TLK111supports an IEEE 1588 indication pulse at the SFD (start frame delimiter) for the RX and TX paths in 100BT mode. The pulse can be delivered to various pins as configured by register 0x3e. The pulse indicates the actual time the symbol is presented on the lines (for TX), or the first bit where the /J/ symbol is received (RX). Exact timing of the pulse can be adjusted using register 0x3f. Each increment of phase value is an 8ns step.
The TLK111 includes an internal power-on-reset (POR) function, and therefore does not need an explicit reset for normal operation after power up.
At power-up, if required by the system, the RESET pin (active low) should be de-asserted 200µs after the power is ramped up to allow the internal circuits to settle and for the internal regulators to stabilize. If required during normal operation, the device can be reset by a hardware or software reset.
A hardware reset is accomplished by applying a low pulse (TTL level), with a duration of at least 1μs, to RESET. This pulse resets the device such that all registers are reinitialized to default values, and the hardware configuration values are re-latched into the device (similar to the power-up/reset operation). The time from the point when the reset pin is de-asserted to the point when the reset has concluded internally is approximately 200µs.
An IEEE registers software reset is accomplished by setting the reset bit (bit 15) of the BMCR register (0x0000h). This bit only resets the IEEE-defined standard registers in the address space 0x00h to 0x07h.
A global software reset is accomplished by setting bit 15 of register PHYRCR (0x001F) to ‘1’. This bit resets all the internal circuits in the PHY including IEEE-defined registers (0x00h to 0x07h) and all the extended registers. The global software reset resets the device such that all registers are reset to default values and the hardware configuration values are maintained.
A global software restart is accomplished by setting bit 14 of register PHYRCR (0x001F) to ‘1’. This action resets all the PHY circuits except the registers in the Register File.
The time from the point when the resets/restart bits are set to the point when the software resets/restart has concluded is approximately 200µs. TI recommends that the software driver code must wait 500µs following software reset before allowing further serial MII operations with the TLK111.
The Power Down and Interrupt functions are multiplexed on pin 7 of the device. By default, this pin functions as a power down input and the interrupt function is disabled. This pin can be configured as an interrupt output pin by setting bit 0 (INT_OE) to ‘1’ in the PHYSCR (0x0011h) register. The PHYSCR register is also used to enable and set the polarity of the interrupt.
The INT/PWDN pin can be asserted low to put the device in a Power Down mode. An external control signal can be used to drive the pin low, overcoming the weak internal pull-up resistor. Alternatively, the device can be configured to initialize into a Power Down state by use of an external pulldown resistor on the INT/PWDN pin.
The interrupt function is controlled via register access. All interrupt sources are disabled by default. The MISR1 (0x0012) and MISR2 (0x0013) registers provide independent interrupt enable bits for the various interrupts supported by the TLK111. The INT/PWDN pin is asynchronously asserted low when an interrupt condition occurs. The source of the interrupt can be determined by reading the interrupt status registers MISR1 (0x0012h) and MISR2 (0x0013). One or more bits in the MISR registers will be set, indicating all currently-pending interrupts. Reading the MISR registers clears ALL pending interrupts.
The TLK111 supports three types of power-save modes. The lowest power consumption is achieved in IEEE power down mode. To enter IEEE power down mode, pull the INT/PWDN pin to LOW or program bit 11 in the Basic Mode Control Register (BMCR), address 0x0000. In this mode all internal circuitry except SMI functionality is shut down (Register access is still available).
To enable and activate all other power save modes through register access, use register PHYSCR (0x0011h). Setting bit 14 enables all power-save modes; bits [13:12] select between them.
Setting bits [13:12] to “01” powers down the PHY, forcing it into IEEE power down mode (Similar to BMCR bit 11 functionality).
Setting bits [13:12] to “10” puts the PHY in Low Power Active Energy Saving mode.
Setting bits [13:12] to “11” puts the PHY in Low Power Passive Energy Saving mode.
When these bits are cleared, the PHY powers up and returns to the last state it was in before it was powered down.
Figure 7-1 shows the recommended circuit for a 10/100Mbs twisted pair interface. Below is a partial list of recommended transformers. Variations with PCB and component characteristics require that the application be tested to verify that the circuit meets the requirements of the intended application.
The TLK111 supports an external CMOS-level oscillator source or an internal oscillator with an external crystal.
If an external clock source is used, XI should be tied to the clock source and XO should be left floating. The amplitude of the oscillator should be a nominal voltage of 3.3V.
The use of a 25MHz, parallel, 20pF-load crystal is recommended if a crystal source is desired. Figure 7-2 shows a typical connection for a crystal resonator circuit. The load capacitor values will vary with the crystal vendors; check with the vendor for the recommended loads.
The oscillator circuit is designed to drive a parallel-resonance AT-cut crystal with a minimum drive level of 100μW and a maximum of 500μW. If a crystal is specified for a lower drive level, a current limiting resistor must be placed in series between XO and the crystal.
As a starting point for evaluating an oscillator circuit, if the requirements for the crystal are not known, set the values for CL1 and CL2 at 33pF, and R1 should be set at 0Ω. Specifications for a 25MHz crystal are listed in Table 7-3.
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT |
---|---|---|---|---|---|
Frequency | 25 | MHz | |||
Frequency Tolerance | Operational Temperature | ±50 | ppm | ||
Frequency Stability | 1 year aging | ±50 | ppm | ||
Rise / Fall Time | 10%–90% | 8 | nsec | ||
Jitter (Short term) | Cycle-to-cycle | 50 | psec | ||
Jitter (Long term) | Accumulative over 10 ms | 1 | nsec | ||
Symmetry | Duty Cycle | 40% | 60% | ||
Load Capacitance | 15 | 30 | pF |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT |
---|---|---|---|---|---|
Frequency | 50 | MHz | |||
Frequency Tolerance | Operational Temperature | ±50 | ppm | ||
Frequency Stability | 1 year aging | ±50 | ppm | ||
Rise / Fall Time | 10%–90% | 6 | nsec | ||
Jitter (Short term) | Cycle-to-cycle | 50 | psec | ||
Jitter (Long term) | Accumulative over 10 ms | 1 | nsec | ||
Symmetry | Duty Cycle | 40% | 60% |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT |
---|---|---|---|---|---|
Frequency | 25 | MHz | |||
Frequency Tolerance | Operational Temperature | ±50 | ppm | ||
At 25°C | ±50 | ppm | |||
Frequency Stability | 1 year aging | ±5 | ppm | ||
Load Capacitance | 10 | 40 | pF |
(Extended temperature (125°C) grade only)
The following thermal via guidelines apply to DOWN_PAD, pin 49:
Adherence to this guideline is required to achieve the intended operating temperature range of the device. Figure 7-3 illustrates an example layout.