SLLSEF8C August   2013  – November 2014 TLK111

PRODUCTION DATA.  

  1. 1  Introduction
    1. 1.1 Features
    2. 1.2 Applications
    3. 1.3 Description
    4. 1.4 Functional Block Diagrams
  2. 2 Pin Descriptions
    1. 2.1 Pin Layout
    2. 2.2 Serial Management Interface (SMI)
    3. 2.3 MAC Data Interface
    4. 2.4 10Mbs and 100Mbs PMD Interface
    5. 2.5 Clock Interface
    6. 2.6 LED Interface
    7. 2.7 JTAG Interface
    8. 2.8 Reset and Power Down
    9. 2.9 Power and Bias Connections
  3. 3 Hardware Configuration
    1. 3.1  Bootstrap Configuration
    2. 3.2  Power Supply Configuration
      1. 3.2.1 Single Supply Operation
      2. 3.2.2 Dual Supply Operation
      3. 3.2.3 Variable IO Voltage
    3. 3.3  IO Pins Hi-Z State During Reset
    4. 3.4  Auto-Negotiation
    5. 3.5  Auto-MDIX
    6. 3.6  PHY Address
    7. 3.7  MII Isolate Mode
    8. 3.8  Software Strapping Mode
    9. 3.9  LED Interface
    10. 3.10 Multi-Configurable LED (MLED)
    11. 3.11 Loopback Functionality
      1. 3.11.1 Near-End Loopback
      2. 3.11.2 Far-End Loopback
    12. 3.12 BIST
    13. 3.13 Cable Diagnostics
      1. 3.13.1 TDR
      2. 3.13.2 ALCD
  4. 4 Interfaces
    1. 4.1 Media Independent Interface (MII)
    2. 4.2 Reduced Media Independent Interface (RMII)
    3. 4.3 Serial Management Interface
      1. 4.3.1 Extended Address Space Access
        1. 4.3.1.1 Write Address Operation
        2. 4.3.1.2 Read Address Operation
        3. 4.3.1.3 Write (no post increment) Operation
        4. 4.3.1.4 Read (no post increment) Operation
        5. 4.3.1.5 Write (post increment) Operation
        6. 4.3.1.6 Read (post increment) Operation
  5. 5 Architecture
    1. 5.1 100Base-TX Transmit Path
      1. 5.1.1 MII Transmit Error Code Forwarding
      2. 5.1.2 4-Bit to 5-Bit Encoding
      3. 5.1.3 Scrambler
      4. 5.1.4 NRZI and MLT-3 Encoding
      5. 5.1.5 Digital to Analog Converter
    2. 5.2 100Base-TX Receive Path
      1. 5.2.1  Analog Front End
      2. 5.2.2  Adaptive Equalizer
      3. 5.2.3  Baseline Wander Correction
      4. 5.2.4  NRZI and MLT-3 Decoding
      5. 5.2.5  Descrambler
      6. 5.2.6  5B/4B Decoder and Nibble Alignment
      7. 5.2.7  Timing Loop and Clock Recovery
      8. 5.2.8  Phase-Locked Loops (PLL)
      9. 5.2.9  Link Monitor
      10. 5.2.10 Signal Detect
      11. 5.2.11 Bad SSD Detection
    3. 5.3 10Base-T Receive Path
      1. 5.3.1 10M Receive Input and Squelch
      2. 5.3.2 Collision Detection
      3. 5.3.3 Carrier Sense
      4. 5.3.4 Jabber Function
      5. 5.3.5 Automatic Link Polarity Detection and Correction
      6. 5.3.6 10Base-T Transmit and Receive Filtering
      7. 5.3.7 10Base-T Operational Modes
    4. 5.4 Auto Negotiation
      1. 5.4.1 Operation
      2. 5.4.2 Initialization and Restart
      3. 5.4.3 Configuration Bits
      4. 5.4.4 Next Page Support
    5. 5.5 Link Down Functionality
    6. 5.6 IEEE 1588 Precision Timing Protocol Support
  6. 6 Reset and Power Down Operation
    1. 6.1 Hardware Reset
    2. 6.2 Software Reset
    3. 6.3 Power Down/Interrupt
      1. 6.3.1 Power Down Control Mode
      2. 6.3.2 Interrupt Mechanisms
    4. 6.4 Power Save Modes
  7. 7 Design Guidelines
    1. 7.1 TPI Network Circuit
    2. 7.2 Clock In (XI) Requirements
      1. 7.2.1 Oscillator
      2. 7.2.2 Crystal
    3. 7.3 Thermal Vias Recommendation
  8. 8 Register Block
    1. 8.1  Register Definition
      1. 8.1.1  Basic Mode Control Register (BMCR)
      2. 8.1.2  Basic Mode Status Register (BMSR)
      3. 8.1.3  PHY Identifier Register 1 (PHYIDR1)
      4. 8.1.4  PHY Identifier Register 2 (PHYIDR2)
      5. 8.1.5  Auto-Negotiation Advertisement Register (ANAR)
      6. 8.1.6  Auto-Negotiation Link Partner Ability Register (ANLPAR) (BASE Page)
      7. 8.1.7  Auto-Negotiate Expansion Register (ANER)
      8. 8.1.8  Auto-Negotiate Next Page Transmit Register (ANNPTR)
      9. 8.1.9  Auto-Negotiation Link Partner Ability Next Page Register (ANLNPTR)
      10. 8.1.10 Software Strap Control register 1 (SWSCR1)
      11. 8.1.11 Software Strap Control register 2 (SWSCR2)
      12. 8.1.12 Software Strap Control Register 3 (SWSCR3)
      13. 8.1.13 Extended Register Addressing
        1. 8.1.13.1 Register Control Register (REGCR)
        2. 8.1.13.2 Address or Data Register (ADDAR)
      14. 8.1.14 Fast Link Down Status Register
      15. 8.1.15 PHY Status Register (PHYSTS)
      16. 8.1.16 PHY Specific Control Register (PHYSCR)
      17. 8.1.17 MII Interrupt Status Register 1 (MISR1)
      18. 8.1.18 MII Interrupt Status Register 2 (MISR2)
      19. 8.1.19 False Carrier Sense Counter Register (FCSCR)
      20. 8.1.20 Receiver Error Counter Register (RECR)
      21. 8.1.21 BIST Control Register (BISCR)
      22. 8.1.22 RMII Control and Status Register (RCSR)
      23. 8.1.23 LED Control Register (LEDCR)
      24. 8.1.24 PHY Control Register (PHYCR)
      25. 8.1.25 10Base-T Status/Control Register (10BTSCR)
      26. 8.1.26 BIST Control and Status Register 1 (BICSR1)
      27. 8.1.27 BIST Control and Status Register2 (BICSR2)
    2. 8.2  Cable Diagnostic Control Register (CDCR)
    3. 8.3  PHY Reset Control Register (PHYRCR)
    4. 8.4  Multi LED Control register (MLEDCR)
    5. 8.5  IEEE1588 Precision Timing Pin Select (PTPPSEL)
    6. 8.6  IEEE1588 Precision Timing Configuration (PTPCFG)
    7. 8.7  TX_CLK Phase Shift Register (TXCPSR)
    8. 8.8  Power Back Off Control Register (PWRBOCR)
    9. 8.9  Voltage Regulator Control Register (VRCR)
    10. 8.10 Cable Diagnostic Configuration/Result Registers
      1. 8.10.1  ALCD Control and Results 1 (ALCDRR1)
      2. 8.10.2  Cable Diagnostic Specific Control Registers (CDSCR1 - CDSCR4)
      3. 8.10.3  Cable Diagnostic Location Results Register 1 (CDLRR1)
      4. 8.10.4  Cable Diagnostic Location Results Register 2 (CDLRR2)
      5. 8.10.5  Cable Diagnostic Location Results Register 3 (DDLRR3)
      6. 8.10.6  Cable Diagnostic Location Results Register 4 (CDLRR4)
      7. 8.10.7  Cable Diagnostic Location Results Register 5 (CDLRR5)
      8. 8.10.8  Cable Diagnostic Amplitude Results Register 1 (CDARR1)
      9. 8.10.9  Cable Diagnostic Amplitude Results Register 2 (CDARR2)
      10. 8.10.10 Cable Diagnostic Amplitude Results Register 3 (CDARR3)
      11. 8.10.11 Cable Diagnostic Amplitude Results Register 4 (CDARR4)
      12. 8.10.12 Cable Diagnostic Amplitude Results Register 5 (CDARR5)
      13. 8.10.13 Cable Diagnostic General Results Register (CDGRR)
      14. 8.10.14 ALCD Control and Results 2 (ALCDRR2)
      15. 8.10.15 ALCD Control and Results 3 (ALCDRR3)
  9. 9 Electrical Specifications
    1. 9.1 Absolute Maximum Ratings
    2. 9.2 Handling Ratings
    3. 9.3 Recommended Operating ConditionsRedundant row "Power dissipation 200 mW"
    4. 9.4 48-Pin Industrial Device Thermal Characteristics
    5. 9.5 48-Pin Extended Temperature (125°C) Device Thermal Characteristics
    6. 9.6 DC Characteristics, VDD_IO DC Characteristics, SD_IN
    7. 9.7 DC Characteristics
    8. 9.8 Power Supply Characteristics
      1. 9.8.1 Active Power, Single Supply Operation
      2. 9.8.2 Active Power, Dual Supply Operation
      3. 9.8.3 Power-Down Power
    9. 9.9 AC Specifications
      1. 9.9.1  Power Up Timing
      2. 9.9.2  Reset Timing
      3. 9.9.3  MII Serial Management Timing
      4. 9.9.4  100Mb/s MII Transmit Timing
      5. 9.9.5  100Mb/s MII Receive Timing
      6. 9.9.6  100Base-TX Transmit Packet Latency Timing
      7. 9.9.7  100Base-TX Transmit Packet Deassertion Timing
      8. 9.9.8  100Base-TX Transmit Timing (tR/F and Jitter)
      9. 9.9.9  100Base-TX Receive Packet Latency Timing
      10. 9.9.10 100Base-TX Receive Packet Deassertion Timing
      11. 9.9.11 10Mbs MII Transmit Timing
      12. 9.9.12 10Mb/s MII Receive Timing
      13. 9.9.13 10Base-T Transmit Timing (Start of Packet)
      14. 9.9.14 10Base-T Transmit Timing (End of Packet)
      15. 9.9.15 10Base-T Receive Timing (Start of Packet)
      16. 9.9.16 10Base-T Receive Timing (End of Packet)
      17. 9.9.17 10Mb/s Jabber Timing
      18. 9.9.18 10Base-T Normal Link Pulse Timing
      19. 9.9.19 Auto-Negotiation Fast Link Pulse (FLP) Timing
      20. 9.9.20 100Base-TX Signal Detect Timing
      21. 9.9.21 100Mbs Loopback Timing
      22. 9.9.22 10Mbs Internal Loopback Timing
      23. 9.9.23 RMII Transmit Timing
      24. 9.9.24 RMII Receive Timing
      25. 9.9.25 Isolation Timing
      26. 9.9.26 25MHz_OUT Clock Timing
  10. 10Revision History, Revision A

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8 Register Block

Table 8-1 Register Map

OFFSET HEX ACCESS TAG DESCRIPTION
00h RW BMCR Basic Mode Control Register
01h RO BMSR Basic Mode Status Register
02h RO PHYIDR1 PHY Identifier Register 1
03h RO PHYIDR2 PHY Identifier Register 2
04h RW ANAR Auto-Negotiation Advertisement Register
05h RO ANLPAR Auto-Negotiation Link Partner Ability Register
06h RO ANER Auto-Negotiation Expansion Register
07h RW ANNPTR Auto-Negotiation Next Page TX
08h RO ANLNPTR Auto-Negotiation Link Partner Ability Next Page Register
09h RW SWSCR1 Software Strap Control Register 1
0Ah RW SWSCR2 Software Strap Control Register 2
0Bh RW SWSCR3 Software Strap Control Register 3
0Ch RW RESERVED RESERVED
0Dh RW REGCR Register control register
0Eh RW ADDAR Address or Data register
0Fh RW FLDS Fast Link Down Status
0x0010 RO PHYSTS PHY Status Register
0x0011 RW PHYSCR PHY Specific Control Register
0x0012 RW MISR1 MII Interrupt Status Register 1
0x0013 RW MISR2 MII Interrupt Status Register 2
0x0014 RO FCSCR False Carrier Sense Counter Register
0x0015 RO RECR Receive Error Count Register
0x0016 RW BISCR BIST Control Register
0x0017 RO RBR RMII and Status Register
0x0018 RW LEDCR LED Control Register
0x0019 RW PHYCR PHY Control Register
0x001A RW 10BTSCR 10Base-T Status/Control Register
0x001B RW BICSR1 BIST Control and Status Register 1
0x001C RO BICSR2 BIST Control and Status Register 2
0x001D RW RESERVED RESERVED
0x001E RW CDCR Cable Diagnostic Control Register
0x001F RW PHYRCR PHY Reset Control Register
EXTENDED REGISTERS
0x0020- 0x0024 RW RESERVED RESERVED
0x0025 RW MLEDCR Multi LED Control register
0x0026- 0x003CD RW RESERVED RESERVED
0x003E RW PTPPSEL IEEE1588 Precision Timing Pin Select
0x003F RW PTPCFG IEEE1588 Precision Timing Configuration
0x0040 RW RESERVED RESERVED
0x0041 RW RESERVED RESERVED
0x0042 RO TXCPSR TX_CLK Phase Shift Register
0x0043- 0x00AD RW RESERVED RESERVED
0x00AE RW PWRBOCR Power Back Off Control Register
0x00AF- 0x00CF RW RESERVED RESERVED
0x00D0 RW VRCR Voltage Regulator Control Register
0x00D1-0x0154 RW RESERVED RESERVED
0x0155 RW ALCDRR1 ALCD Control and Results 1
0x0156- 0x016F RW RESERVED RESERVED
0x0170 RW CDSCR1 Cable Diagnostic Specific Control Register 1
0x0171 RW CDSCR2 Cable Diagnostic Specific Control Register 2
0x0172 RW RESERVED RESERVED
0x0173 RW CDSCR3 Cable Diagnostic Specific Control Register 3
0x0174-0x0176 RW RESERVED RESERVED
0x0177 RW CDSCR4 Cable Diagnostic Specific Control Register 4
0x0178- 0x017F RW RESERVED RESERVED
0x0180 RO CDLRR1 Cable Diagnostic Location Result Register 1
0x0181 RO CDLRR2 Cable Diagnostic Location Result Register 2
0x0182 RO CDLRR3 Cable Diagnostic Location Result Register 3
0x0183 RO CDLRR4 Cable Diagnostic Location Result Register 4
0x0184 RO CDLRR5 Cable Diagnostic Location Result Register 5
0x0185 RO CDLAR1 Cable Diagnostic Amplitude Result Register 1
0x0186 RO CDLAR2 Cable Diagnostic Amplitude Result Register 2
0x0187 RO CDLAR3 Cable Diagnostic Amplitude Result Register 3
0x0188 RO CDLAR4 Cable Diagnostic Amplitude Result Register 4
0x0189 RO CDLAR5 Cable Diagnostic Amplitude Result Register 5
0x018A RW CDGRR Cable Diagnostic General Result Register
0x018B-0x0214 RW RESERVED RESERVED
0x0215 RW ALCDRR2 ALCD Control and Results 2 Register
0x021D RW ALCDRR3 ALCD Control and Results 3 Register

Table 8-2 Register Table

Register Name Addr Tag Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Basic Mode Control Register 00h BMCR Reset Loopback Speed Selection Auto-Neg Enable IEEE Power Down Isolate Restart Auto-Neg Duplex Mode Collision Test Reserved
Basic Mode Status Register 01h BMSR 100Base -T4 100Base -TX FDX 100Base -TX HDX 10Base-T FDX 10Base-T HDX Reserved MF Preamble Suppress Auto-Neg Complete Remote Fault Auto-Neg Ability Link Status Jabber Detect Extended Capability
PHY Identifier Register 1 02h PHYIDR 1 OUI MSB
PHY Identifier Register 2 03h PHYIDR 2 OUI LSB VNDR_ MDL MDL_ REV
Auto-Negotiation Advertisement Register 04h ANAR Next Page Ind Reserved Remote Fault Reserved ASM_DI R PAUSE 100B-T4 100B-TX_FD 100B-TX 10B-T_FD 10B-T Protocol Selection[4:0]
Auto-Negotiation Link Partner Ability Register (Base Page) 05h ANLPAR Next Page Ind ACK Remote Fault Reserved ASM_DI R PAUSE 100B-T4 100B-TX_FD 100B-TX 10B-T_FD 10B-T Protocol Selection[4:0]
Auto-Negotiation Expansion Register 06h ANER Reserved PDF LP_NP_ ABLE NP_ ABLE PAGE_ RX LP_AN_ABLE
Auto-Negotiation Next Page TX Register 07h ANNPTR Next Page Ind Reserved Message Page ACK2 TOG_TX CODE
Auto-Negotiate Link Partner Ability Page Register 08h ANLNPTR Next Page Ind Reserved Message Page ACK2 Toggle CODE
Control Register 1 09h CR1 Reserved RMII Enhance Mode TDR Auto Run Link Loss Recovery Fast Auto MDI/X Robust Auto MDI/X Fast AN Enable Fast AN Select Fast RXDV Detect Reserved
Software Strap Control Register 2 0Ah SWSCR2 100BT Force Far-End Link drop Reserved Fast Link-Up in PD Extended FD Ability Enhance LED Link Isolate MII in 100BT HD RXERR During IDLE Odd Nibble Detect Disable RMII Receive Clock
Control Register 3 0Bh CR3 Reserved Fast Link Down Mode Reserved Polarity Swap MDI/X Swap Reserved Fast Link Down Sel
Register Control Register 0Dh REGCR Function Reserved DEVICE ADDRESS
Address or Data Register 0Eh ADDAR Addr/ Data
Fast Link Down Status 0Fh FLDS Reserved Fast Link Down Status[4:0] Reserved
PHY Status Register 10h PHYSTS Reserved MDI-X Mode Receive Err Latch Polarity Status False Carrier Sen Latch Signal Detect Descramb Lock Page Receive MII Interrupt Remote Fault Jabber Detect Auto-Neg Status Loopback Status Duplex Status Speed Status Link Status
PHY Specific Control Register 11h PHYSCR Disable PLL Power Save Enable Power Save Mode Scrambler Bypass Reserved Loopback Fifo Depth Reserved COL FD Enable INT POL TINT INT_EN INT_OE
MII Interrupt Status Register 1 12h MISR1 Reserved Link Status INT Speed INT Duplex Mode INT Auto-Neg Comp INT FC HF INT RE HF INT Reserved Link Status En Speed EN Duplex Mode En Auto-Neg Comp En FC HF En RE HF En
MII Interrupt Status Register 2 13h MISR2 Reserved Auto-Neg Error INT Page Received INT Loopback FIFO O/U INT MDI Crossover INT Sleep Mode INT Polarity INT Jabber INT Reserved Auto-Neg Error EN Page Received EN Loopback FIFO O/U EN MDI Crossover EN Sleep Mode EN Polarity EN Jabber EN
MII Interrupt Control Register 14h FCSCR Reserved FCS Count
Receive Error Counter Register 15h RECR RX Err Count
BIST Control Register 16h BISCR Reserved PRBS Count Mode Generate PRBS Packets Packet Gen Enable PRBS Checker Lock PRBS Checker SyncLoss Packet Gen Status Power Mode Reserved Transmit in MII Loopback Reserved Loopback Mode
RMII Control, Status Register 17h RCSR Reserved RMII Mode RMII Revision RMII OVF Status RMII UNF Status ELAST BUF
LED Control Register 18h LEDCR Reserved Blink Rate LED Speed Polarity LED Link Polarity LED Activity Polarity Drive LED Speed Drive LED Link Drive LED Activity Speed LED ON/OFF Link LED ON/OFF Activity LED ON/OFF
PHY Control Register 19h PHYCR Auto MDI/X Enable Force MDI/X Pause RX Status Pause TX Status MI Link Status Reserved Bypass LED Stretching LED CFG PHY ADDR
BIST Packet Length register 1Ah 10BTSCR Reserved Receiver TH Squelch Reserved NLP Disable Reserved Polarity Status Reserved Jabber Disable
BIST Control, Status Register 1 1Bh BICSR1 BIST Err Count BIST IPG Length
BIST Control, Status Register 2 1Ch BICSR2 Reserved Packet Length
Cable Diagnostic Control Register 1Eh CDCR Diagnostic Start Reserved Link Quality Link Quality Reserved Diagnostic Done Diagnostic Fail
Power Down Register 1Fh PDR Software Reset Software Restart Reserved

Table 8-3 Register Table, Extended Registers

Register Name Addr Tag Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Multi LED Control 25h MLED Reserved MLED pin 42 Route, Enable (COL Disable) MLED Polarity Reserved MLED Configuration Reserved MLED pin 28 Routing Cnfig. "MLED pin Routing enable"
1588 PTP Pin Select 3Eh PTPPSEL Reserved cfg_1588_TX_pin_sel Reserved cfg_1588_RX_pin_sel
1588 PTP Config 3Fh PTPCFG cfg_1588_TX_set_phase cfg_1588_RX_set_phase cfg_TX_ERR_sel Reserved
TX_CLK 42h TXCPSR Reserved Phase Shift En Phase Shift Value
Voltage Regulator Control Register D0h VRCR VRPD Reserved VR Control
PowerBack Off Control Register AEh PWRBOCR Reserved PowerBack Off Reserved
ALCD Control and Results 1 155h ALCDRR1 alcd_start Reserved alcd_done alcd_out1 Reserved alcd_ctrl
Cable Diagnostic Specific Control Register 1 170h CDSCR1 Reserved Cross Disable TPTD Bypass TPRD Bypass Reserved Average Cycles Reserved
Cable Diagnostic Specific Control Register 2 171h CDSCR2 Reserved TDR pulse control
Cable Diagnostic Specific Control Register 3 173h CDSCR3 Cable length Reserved
Cable Diagnostic Specific Control Register 4 177h CDSCR4 Short cables TH Reserved
Cable Diagnostic Location Results Register 1-5 180h CDLRR1 TPTD/RD Peak Location
181h CDLRR2
182h CDLRR3
183h CDLRR4
184h CDLRR5
Cable Diagnostic Amplitude Results Register 1-5 185h CDLAR1 Reserved TPTD/RD Peak Amplitude Reserved TPTD/RD Peak Amplitude
186h CDLAR2
187h CDLAR3
188h CDLAR4
189h CDLAR5
Cable Diagnostic General Results 18Ah CDGRR TPTD Peak Polarity 5 TPTD Peak Polarity 4 TPTD Peak Polarity 3 TPTD Peak Polarity 2 TPTD Peak Polarity 1 TPRD Peak Polarity 5 TPRD Peak Polarity 4 TPRD Peak Polarity 3 TPRD Peak Polarity 2 TPRD Peak Polarity 1 Cross Detect on TPTD Cross Detect on TPRD Above 5 TPTD Peaks Above 5 TPTD Peaks Reserved Reserved
ALCD Control and Results 2 215h ALCDRR2 Reserved alcd_out2
ALCD Control and Results 3 21Dh ALCDRR3 Reserved FAGC Accumulator

8.1 Register Definition

In the register definitions under the ‘Default’ heading, the following definitions hold true:

  • COR = Clear on Read
  • Pin_Strap = Default value loads from strapping pin after reset
  • LH = Latched High and held until read, based upon the occurrence of the corresponding event
  • LL = Latched Low and held until read, based upon the occurrence of the corresponding event
  • RO = Read Only access
  • RO/COR = Read Only, Clear on Read
  • RO/P = Read Only, Permanently set to a default value
  • RW = Read Write access
  • RW/SC = Read Write Access/Self Clearing bit
  • SC = Register sets on event occurrence and Self-Clears when event ends
  • SWSC_Strap = Default value loads from SWSC strapping bit
  • SWS = Software Strap bit: Bit is always accessible. When written during soft strap mode, latches value after applying Config Done; acts as Default during functional mode (until next HW Reset). Otherwise, latches bit content regularly as RW.
  • SWSC = Software Strap config - Bit is accessible only at Software strap mode, value of bit is latched after applying Config Done as default to the destination bit. During functional mode the bit is not accessible. The SWSC duplicate external pin strap option, in this case SWSC has higher priority than the pin Configuration. SWSC default value will come from the corresponding pin Configuration

8.1.1 Basic Mode Control Register (BMCR)

Table 8-4 Basic Mode Control Register (BMCR), address 0x0000

BIT BIT NAME DEFAULT DESCRIPTION
15 Reset 0, RW/SC PHY Software Reset:
1 = Initiate software Reset / Reset in Process
0 = Normal operation

Writing a 1 to this bit resets the PHY. When the reset operation is done, this bit is cleared to 0 automatically. The configuration is relatched.
14 MII Loopback 0, RW MII Loopback:
1 = MII Loopback enabled
0 = Normal operation
When MII loopback mode is activated, the transmitter data presented on MII TXD is looped back to MII RXD internally.
13 Speed Selection 1, Pin_Strap, SWSC_Strap, RW Speed Select:
When auto-negotiation is disabled writing to this bit allows the port speed to be selected.
1 = 100Mbs
0 = 10Mbs
12 Auto-Negotiation Enable 1, Pin_Strap, SWSC_Strap, RW Auto-Negotiation Enable:
Configuration pin (jumper) controls initial value at reset.
1 = Auto-Negotiation Enabled – bits 8 and 13 of this register are ignored when this bit is set.
0 = Auto-Negotiation Disabled – bits 8 and 13 determine the port speed and duplex mode.
11 IEEE Power Down 0, RW Power Down:
1 = Enables IEEE power down mode
0 = Normal operation
Setting this bit powers down the PHY. Only minimal register functionality is enabled during the power down condition. To control the power down mechanism, this bit is ORed with the input from the INT/PWDN pin. When the active low INT/PWDN is asserted, this bit is set.
10 Isolate 0, RW Isolate:
1 = Isolates the Port from the MII with the exception of the serial management
0 = Normal operation
9 Restart Auto- Negotiation 0, RW/SC Restart Auto-Negotiation:
1 = Restart Auto-Negotiation. Re-initiates the Auto-Negotiation process. If Auto-Negotiation is disabled (bit 12 = 0), this bit is ignored. This bit is self-clearing and will return a value of 1 until Auto-Negotiation is initiated, whereupon it will self-clear. Operation of the Auto-Negotiation process is not affected by the management entity clearing this bit.
0 = Normal operation
Re-initiates the Auto-Negotiation process. If Auto-Negotiation is disabled (bit 12 = 0), this bit is ignored. This bit is self-clearing and will return a value of 1 until Auto-Negotiation is initiated, whereupon it self-clears. Operation of the Auto-Negotiation process is not affected by the management entity clearing this bit.
8 Duplex Mode 1, Pin_Strap, SWSC_Strap, RW Duplex Mode:
When auto-negotiation is disabled writing to this bit allows the port Duplex capability to be selected.
1 = Full Duplex operation
led control 0 = Half Duplex operation
7 Collision Test 0, RW Collision Test:
1 = Collision test enabled
0 = Normal operation
When set, this bit causes the COL signal to be asserted in response to the assertion of TX_EN within 512 bit times. The COL signal is de-asserted within 4 bit times in response to the de-assertion of TX_EN.
6:0 RESERVED 0, RO RESERVED: Write ignored, read as 0.

8.1.2 Basic Mode Status Register (BMSR)

Table 8-5 Basic Mode Status Register (BMSR), address 0x0001

BIT BIT NAME DEFAULT DESCRIPTION
15 100Base-T4 0, RO/P 100Base-T4 Capable:
This protocol is not available. Always 0 = Device does not perform 100Base-T4 mode.
14 100Base-TX Full Duplex 1, RO/P 100Base-TX Full Duplex Capable:
1 = Device able to perform 100Base-TX in full duplex mode
0 = Device not able to perform 100Base-TX in full duplex mode
13 100Base-TX Half Duplex 1, RO/P 100Base-TX Half Duplex Capable:
1 = Device able to perform 100Base-TX in half duplex mode
0 = Device not able to perform 100Base-TX in half duplex mode
12 10Base-T
Full Duplex		 1, RO/P 10Base-T Full Duplex Capable:
1 = Device able to perform 10Base-T in full duplex mode
0 = Device not able to perform 10Base-T in full duplex mode
11 10Base-T Half Duplex 1, RO/P 10Base-T Half Duplex Capable:
1 = Device able to perform 10Base-T in half duplex mode
0 = Device not able to perform 10Base-T in half duplex mode
10:7 RESERVED 0, RO RESERVED: Write as 0, read as 0
6 MF Preamble Suppression 1, RO/P Preamble suppression Capable:
1 = Device able to perform management transaction with preamble suppressed, 32-bits of preamble needed only once after reset, invalid opcode or invalid turnaround.
0 = Device will not perform management transaction with preambles suppressed
5 Auto-Negotiation Complete 0, RO Auto-Negotiation Complete:
1 = Auto-Negotiation process complete
0 = Auto-Negotiation process not complete (either still in process, disabled, or reset)
4 Remote Fault 0, RO/LH Remote Fault:
1 = Remote Fault condition detected (cleared on read or by reset). Fault criteria: Far End Fault Indication or notification from Link Partner of Remote Fault.
0 = No remote fault condition detected
3 Auto-Negotiation Ability 1, RO/P Auto Negotiation Ability:
1 = Device is able to perform Auto-Negotiation
0 = Device is not able to perform Auto-Negotiation
2 Link Status 0, RO/LL Link Status:
1 = Valid link established (for either 10 or 100Mbs operation)
0 = Link not established
1 Jabber Detect 0, RO/LH Jabber Detect: This bit only has meaning in 10Mbs mode.
1 = Jabber condition detected
0 = No Jabber. condition detected
This bit is implemented with a latching function, such that the occurrence of a jabber condition causes it to set until it is cleared by a read to this register by the management interface or by a reset.
0 Extended Capability 1, RO/P Extended Capability:
1 = Extended register capabilities
0 = Basic register set capabilities only

8.1.3 PHY Identifier Register 1 (PHYIDR1)

The PHY Identifier Registers 1 and 2 together form a unique identifier for the TLK111. The identifier consists of a concatenation of the Organizationally Unique Identifier (OUI), the vendor's model number and the model revision number. A PHY may return a value of zero in each of the 32 bits of the PHY Identifier if desired. The PHY Identifier is intended to support network management. The Texas Instruments IEEE-assigned OUI is 080028h, implemented as Reg 0x2 [15:0] = OUI[21:6] = 2000(h) and Reg 0x3 [15:10] = OUI[5:0] = A(h).

Table 8-6 PHY Identifier Register 1 (PHYIDR1), address 0x0002

BIT BIT NAME DEFAULT DESCRIPTION
15:0 OUI_MSB 0010 0000 0000 0000,
RO/P		 OUI[21:6] = 2000(h): The most significant two bits of the OUI are ignored (the IEEE standard refers to these as bits 1 and 2).

8.1.4 PHY Identifier Register 2 (PHYIDR2)

Table 8-7 PHY Identifier Register 2 (PHYIDR2), address 0x0003

BIT BIT NAME DEFAULT DESCRIPTION
15:10 OUI_LSB 1010 00, RO/P OUI[5:0] = 28(h)
9:4 VNDR_MDL 10 0001, RO/P Vendor Model Number:

The six bits of vendor model number are mapped from bits 9 to 4 (most significant bit to bit 9).
3:0 MDL_REV 0010, RO/P Model Revision Number:

Four bits of the vendor model revision number are mapped from bits 3 to 0 (most significant bit to bit 3). This field is incremented for all major device changes.

8.1.5 Auto-Negotiation Advertisement Register (ANAR)

This register contains the advertised abilities of this device as they are transmitted to its link partner during Auto-Negotiation.

Table 8-8 Auto Negotiation Advertisement Register (ANAR), address 0x0004

BIT BIT NAME DEFAULT DESCRIPTION
15 NP 0, RW Next Page Indication:
0 = Next Page Transfer not desired
1 = Next Page Transfer desired
14 RESERVED 0, RO/P RESERVED by IEEE: Writes ignored, Read as 0
13 RF 0, RW Remote Fault:
1 = Advertises that this device has detected a Remote Fault
0 = No Remote Fault detected
12 RESERVED 0, RW RESERVED for Future IEEE use: Write as 0, Read as 0
11 ASM_DIR 0, RW Asymmetric PAUSE Support for Full Duplex Links: The ASM_DIR bit indicates that asymmetric PAUSE is supported.
1 = Asymmetric PAUSE implemented. Advertise that the DTE/MAC has implemented both the optional MAC control sublayer and the pause function as specified in clause 31 and annex 31B of IEEE802.3u.
0 = Asymmetric PAUSE not implemented
Encoding and resolution of PAUSE bits is defined in IEEE 802.3 Annex 28B, Tables 28B-2 and 28B-3, respectively. Pause resolution status is reported in PHYCR[13:12].
10 PAUSE 0, RW PAUSE Support for Full Duplex Links: The PAUSE bit indicates that the device is capable of providing the symmetric PAUSE functions as defined in Annex 31B.
1 = MAC PAUSE implemented. Advertise that the DTE (MAC) has implemented both the optional MAC control sub-layer and the pause function as specified in clause 31 and annex 31B of 802.3u.
0 = MAC PAUSE not implemented
Encoding and resolution of PAUSE bits is defined in IEEE 802.3 Annex 28B, Tables 28B-2 and 28B-3, respectively. Pause resolution status is reported in PHYCR[13:12].
9 100B-T4 0, RO/P 100Base-T4 Support:
1 = 100Base-T4 is supported by the local device
0 = 100Base-T4 not supported
8 100B-TX_FD 1, Pin_Strap, SWSC_Strap, RW 100Base-TX Full Duplex Support:
1 = 100Base-TX Full Duplex is supported by the local device
0 = 100Base-TX Full Duplex not supported
7 100B-TX 1, Pin_Strap, SWSC_Strap, RW 100Base-TX Support:
1 = 100Base-TX is supported by the local device
0 = 100Base-TX not supported
6 10B-T_FD 1, Pin_Strap, SWSC_Strap, RW 10Base-T Full Duplex Support:
1 = 10Base-T Full Duplex is supported by the local device
0 = 10Base-T Full Duplex not supported
5 10B-T 1, Pin_Strap, SWSC_Strap, RW 10Base-T Support:
1 = 10Base-T is supported by the local device
0 = 10Base-T not supported
4:0 Selector 0 0001, RW Protocol Selection Bits:

These bits contain the binary encoded protocol selector supported by this port. <00001> indicates that this device supports IEEE 802.3u.

8.1.6 Auto-Negotiation Link Partner Ability Register (ANLPAR) (BASE Page)

This register contains the advertised abilities of the Link Partner as received during Auto-Negotiation. The content changes after the successful auto-negotiation if Next-pages are supported.

Table 8-9 Auto-Negotiation Link Partner Ability Register (ANLPAR) (BASE Page), address 0x0005

BIT BIT NAME DEFAULT DESCRIPTION
15 NP 0, RO Next Page Indication:
0 = Link Partner does not desire Next Page Transfer
1 = Link Partner desires Next Page Transfer
14 ACK 0, RO Acknowledge:
1 = Link Partner acknowledges reception of the ability data word
0 = Not acknowledged. The Auto-Negotiation state machine will automatically control the this bit based on the incoming FLP bursts.
13 RF 0, RO Remote Fault:
1 = Remote Fault indicated by Link Partner
0 = No Remote Fault indicated by Link Partner
12 RESERVED 0, RO RESERVED for Future IEEE use: Write as 0, read as 0
11 ASM_DIR 0, RO ASYMMETRIC PAUSE:
1 = Asymmetric pause is supported by the Link Partner
0 = Asymmetric pause is not supported by the Link Partner
10 PAUSE 0, RO PAUSE:
1 = Pause function is supported by the Link Partner
0 = Pause function is not supported by the Link Partner
9 100B-T4 0, RO 100Base-T4 Support:
1 = 100Base-T4 is supported by the Link Partner
0 = 100Base-T4 is not supported by the Link Partner
8 100B-TX_FD 0, RO 100Base-TX Full Duplex Support:
1 = 100Base-TX Full Duplex is supported by the Link Partner
0 = 100Base-TX Full Duplex is not supported by the Link Partner
7 100B-TX 0, RO 100Base-TX Support:
1 = 100Base-TX is supported by the Link Partner
0 = 100Base-TX is not supported by the Link Partner
6 10B-T_FD 0, RO 10Base-T Full Duplex Support:
1 = 10Base-T Full Duplex is supported by the Link Partner
0 = 10Base-T Full Duplex is not supported by the Link Partner
5 10B-T 0, RO 10Base-T Support:
1 = 10Base-T is supported by the Link Partner
0 = 10Base-T is not supported by the Link Partner
4:0 Selector 0 0000, RO Protocol Selection Bits:

Link Partner’s binary encoded protocol selector.

8.1.7 Auto-Negotiate Expansion Register (ANER)

This register contains additional Local Device and Link Partner status information.

Table 8-10 Auto-Negotiate Expansion Register (ANER), address 0x0006

BIT BIT NAME DEFAULT DESCRIPTION
15:5 RESERVED 0, RO RESERVED: Writes ignored, Read as 0.
4 PDF 0, RO Parallel Detection Fault:
1 = Fault detected via the Parallel Detection function
0 = No fault detected
3 LP_NP_ABLE 0, RO Link Partner Next Page Able:
1 = Link Partner does support Next Page
0 = Link Partner does not support Next Page
2 NP_ABLE 1, RO/P Next Page Able:
1 = Indicates local device is able to send additional Next Pages
0 = Indicates local device is not able to send additional Next Pages
1 PAGE_RX 0, RO/COR Link Code Word Page Received:
1 = Link Code Word has been received, cleared on a read
0 = Link Code Word has not been received
0 LP_AN_ABLE 0, RO Link Partner Auto-Negotiation Able:
1 = indicates that the Link Partner supports Auto-Negotiation
0 = indicates that the Link Partner does not support Auto-Negotiation

8.1.8 Auto-Negotiate Next Page Transmit Register (ANNPTR)

This register contains the next page information sent by this device to its Link Partner during Auto-Negotiation.

Table 8-11 Auto-Negotiation Next Page Transmit Register (ANNPTR), address 0x0007

BIT BIT NAME DEFAULT DESCRIPTION
15 NP 0, RW Next Page Indication:
0 = No other Next Page Transfer desired
1 = Another Next Page desired
14 RESERVED 0, RO RESERVED: Writes ignored, read as 0
13 MP 1, RW Message Page:
1 = Message Page
0 = Unformatted Page
12 ACK2 0, RW Acknowledge2:
1 = Will comply with message
0 = Cannot comply with message
Acknowledge2 is used by the next page function to indicate that Local Device has the ability to comply with the message received.
11 TOG_TX 0, RO Toggle:
1 = Value of toggle bit in previously transmitted Link Code Word was 0
0 = Value of toggle bit in previously transmitted Link Code Word was 1
Toggle is used by the Arbitration function within Auto-Negotiation to synchronize with the Link Partner during Next Page exchange. This bit always takes the opposite value of the Toggle bit in the previously exchanged Link Code Word.
10:0 CODE 000 0000 0001,
RW		 This field represents the code field of the next page transmission. If the MP bit is set (bit 13 of this register), then the code is interpreted as a Message Page, as defined in annex 28C of IEEE 802.3u. Otherwise, the code is interpreted as an Unformatted Page, and the interpretation is application specific.

The default value of the CODE represents a Null Page as defined in Annex 28C of IEEE 802.3u.

8.1.9 Auto-Negotiation Link Partner Ability Next Page Register (ANLNPTR)

This register contains the next page information sent by this device to its Link Partner during Auto-Negotiation.

Table 8-12 Auto-Negotiation Link Partner Ability Register Next Page (ANLNPTR), address 0x0008

BIT BIT NAME DEFAULT DESCRIPTION
15 NP 0, RO Next Page Indication:
1 = No other Next Page Transfer desired
0 = Another Next Page desired
14 ACK 0, RO Acknowledge:
1 = Link Partner acknowledges reception of the ability data word
0 = Not acknowledged
The Auto-Negotiation state machine automatically controls this bit based on the incoming FLP bursts. Software should not attempt to write to this bit.
13 MP 1, RO Message Page:
1 = Message Page
0 = Unformatted Page
12 ACK2 0, RO Acknowledge2:
1 = Link Partner has the ability to comply to next-page message
0 = Link Partner cannot comply to next-page message
Acknowledge2 is used by the next page function to indicate that Local Device has the ability to comply with the message received.
11 Toggle 0, RO Toggle:
1 = Value of toggle bit in previously transmitted Link Code Word was 0
0 = Value of toggle bit in previously transmitted Link Code Word was 1
Toggle is used by the Arbitration function within Auto-Negotiation to synchronize with the Link Partner during Next Page exchange. This bit always takes the opposite value of the Toggle bit in the previously exchanged Link Code Word.
10:0 CODE 000 0000 0001, RO Code:

This field represents the code field of the next page transmission. If the MP bit is set (bit 13 of this register), then the code is interpreted as a Message Page, as defined in annex 28C of IEEE 802.3u. Otherwise, the code is interpreted as an Unformatted Page, and the interpretation is application specific.

The default value of the CODE represents a Null Page as defined in Annex 28C of IEEE 802.3u.

8.1.10 Software Strap Control register 1 (SWSCR1)

This register contains the configuration bits used as strapping options or virtual strapping pins during HW RESET. These configuration values are programmed by the system processor after HW_RESET/POR, and then the “Config Done” - bit 15 of register SWSCR1 (0x0009) is set at the end of the configuration. An internal reset pulse is generated and the SW Strap bit values are latched into internal registers.

Table 8-13 SW Strap Control register 1 (SWSCR1), address 0x0009

BIT BIT NAME DEFAULT DESCRIPTION
15 SW Strap Config Done 0, RW Software Strap Configuration Done:
1 = SW Strap configuration is complete, and the PHY can continue and complete its internal reset sequence.
0 = SW strap configuration process is not complete
14 Auto MDI-X Enable 1, SWSC, RW Auto MDI/MDIX Enable:
1 = Enable automatic crossover
0 = Disable automatic crossover
This bit determines whether Automatic MDI/MDIX crossover is enabled or not. If Strapping Pin configuration is override, the value of this register is latched at RESET to bit 15 of PHYCR register (0x0019) and defines its value.
13 Auto-Negotiation Enable 1, SWSC, RW Auto-Negotiation Enable:
1 = Auto-Negotiation Enabled
0 = Auto-Negotiation Disabled – Force mode is active
This bit determines whether Auto-negotiation is enabled
12:11 AN[1:0] 1, SWSC, RW Auto-Negotiation Mode [1:0]:
ANEN AN_1 AN_0 Forced Mode
0 0 0 10Base-T, Half-Duplex
0 0 1 10Base-T, Full-Duplex
0 1 0 100Base-TX, Half-Duplex
0 1 1 100Base-TX, Full-Duplex
ANEN AN_1 AN_0 Advertised Mode
1 0 0 10Base-T, Half or Full-Duplex
1 0 1 100Base-TX, Half or Full-Duplex
1 1 0 10Base-T,Half-Duplex
100Base-TX, Half-Duplex
1 1 1 10Base-T,Half or Full-Duplex
100Base-TX, Half or Full-Duplex
If the Strapping Pin configuration is override, the decoded value of these 3 register bits are latched at RESET to the appropriate bits of BMCR (0x0000) and ANAR (0x0004) and define their values.
10 LED_CFG 1, SWSC, RW LED Configuration:
1 = Select LED configuration Mode 1
0 = Select LED configuration Mode 2 or 3 according to LEDCR register (0x0018) bit 5 and 6.
If the Strapping Pin configuration is override, the value of this register is latched at RESET to bit 5 of the PHYCR register (0x0019) and defines its value.
9 RMII Enhanced Mode 0, SWS, RW RMII Enhanced Mode:
1 = Enable RMII Enhanced Mode
0 = RMII operates in normal mode
In normal mode, If the line is not idle CRS_DV goes high. As soon as the False Carrier is detected, RX_ER is asserted and RXD is set to “2”. This situation remains for the duration of the receive event. While in enhanced mode, CRS_DV is disqualified and de-asserted when the False Carrier detected. This status also remains for the duration of the receive event. In addition in normal mode, the start of the packet is intact. Each symbol error is indicated by setting RX_ER high. The data on RXD is replaced with “1” starting with the first symbol error. While in enhanced mode, the CRS_DV is de-asserted with the first symbol error.
8 TDR AUTORUN 0, SWS, RW TDR Auto Run at link down:
1 = Enable execution of TDR procedure after link down event
0 = Disable automatic execution of TDR
7 Link Loss Recovery 0, SWS, RW Link Loss Recovery:
1 = Enable Link Loss Recovery mechanism. This mode allow recovery from short interference and continue to hold the link up for period of additional few mSec till the short interference will gone and the signal is OK.
0 = Normal Link Loss operation. Link status will go down approximately 250µs from signal loss.
6 Fast Auto MDI-X 0, SWS, RW Fast Auto MDI/MDIX:
1 = Enable Fast Auto MDI/MDIX mode
0 = Normal Auto MDI/MDIX mode.
If both link partners are configured to work in Force 100Base-TX mode (Auto-Negotiation is disabled), this mode enables Automatic MDI/MDIX resolution in a short time.
5 Robust Auto MDI-X 0, SWS, RW Robust Auto MDI-X :
1 = Enable Robust Auto MDI/MDIX resolution
0 = Normal Auto MDI/MDIX mode
If link partners are configured to operational modes that are not supported by normal Auto MDI/MDIX mode (like Auto-Neg versus Force 100Base-TX or Force 100Base-TX versus Force 100Base-TX), this Robust Auto MDI/MDIX mode allows MDI/MDIX resolution and prevents deadlock.
4 Fast AN En 0, SWS, RW Fast AN En:
1 = Enable Fast Auto-Negotiation mode – The PHY auto-negotiates using Timer setting according to Fast AN Sel bits (bits 3:2 this register)
0 = Disable Fast Auto-Negotiation mode – The PHY auto-negotiates using normal Timer setting
Adjusting these bits reduces the time it takes to Auto-negotiate between two PHYs. Note: When using this option care must be taken to maintain proper operation of the system. While shortening these timer intervals may not cause problems in normal operation, there are certain situations where this may lead to problems.
3:2 Fast AN Sel 0, SWS, RW Fast Auto-Negotiation Select bits:
Fast AN Select Break Link Timer Link Fail Inhibit Timer Auto-Neg Wait Timer
<00> 80 50 35
<01> 120 75 50
<10> 240 150 100
<11> NA NA NA
Adjusting these bits reduces the time it takes to Auto-negotiate between two PHYs. In Fast AN mode, both PHYs should be configured to the same configuration. These 2 bits define the duration for each state of the Auto Negotiation process according to the table above. The new duration time must be enabled by setting “Fast AN En” - bit 4 of this register. Note: Using this mode in cases where both link partners are not configured to the same Fast Auto-negotiation configuration might produce scenarios with unexpected behavior.
1 Fast RXDV Detection 0, SWS, RW Fast RXDV Detection:
1 = Enable assertion high of RX_DV on receive packet due to detection of /J/ symbol only. If a consecutive /K/ does not appear, RX_ER is generated.
0 = Disable Fast RX_DV detection. The PHY operates in normal mode - RX_DV assertion after detection of /J/K/.
0 INT OE 0, SWS, RW INT/PWDN Enable:
1 = INT/PWDN Pin is an open-drain Interrupt Output.
0 = INT/PWDN Pin is active-low Power Down input.
RESET (applied after SW Strap Config. finishes) latches the value of this register bit to bit 0 of the PHYSCR register (0x0011); this defines the PHYSCR[0] value. The INT OE bit, as opposed to other SWSC bits, has no external pin to determine the default value. The INT OE default value is always zero, unless changed during SW strap configuration mode.

8.1.11 Software Strap Control register 2 (SWSCR2)

This register contains the configuration bits used as strapping options or virtual strapping pins during HW RESET. These configuration values are programmed by the system processor after HW_RESET/POR, and then the “Config Done” - bit 15 of register SWSCR1 (0x0009) is set at the end of the configuration. An internal reset pulse is generated and the SW Strap bit values are latched into internal registers.

Table 8-14 SW Strap Control register 2 (SWSCR2), address 0x000A

BIT BIT NAME DEFAULT DESCRIPTION
15 100BT Force Far-End Link drop 0, RW 100BT Force Far-End Link drop: Writing a 1 asserts the 100BT Force Far-End link drop mode. In this mode (only valid in force 100BT), the PHY disables the TX upon link drop to allow the far-end peer to drop its link as well, thus allowing both link partners be aware of the system link failure. This mode exceeds the standard definition of force 100BT.
14 RESERVED 0, RW RESERVED
13:7 RESERVED 2, SWS, RW RESERVED
6 Fast Link-Up in Parallel Detect 0, SWS, RW Fast Link-Up in Parallel Detect Mode:
1 = Enable Fast Link-Up time During Parallel Detection
0 = Normal Parallel Detection link establishment
In Fast Auto MDI-X and in Robust Auto MDI-X modes (bits 6 and 5 in register SWSCR1), this bit is automatically set.
5 Extended FD Ability 0, SWS, RW Extended Full-Duplex Ability:
1 = Force Full-Duplex while working with link partner in forced 100B-TX. When the PHY is set to Auto-Negotiation or Force 100B-TX and the link partner is operated in Force 100B-TX, the link is always Full Duplex
0 = Disable Extended Full Duplex Ability. Decision to work in Full Duplex or Half Duplex mode follows IEEE specification.
4 Enhanced LED Link 0, SWS, RW Enhanced LED Link Functionality:
1 = LED Link is ON only when link is established in 100B-TX Full Duplex mode.
0 = LED Link is ON when link is established.
3 Isolate MII in 100BT HD 0, SWS, RW Isolate MII outputs when FD Link @ 100BT is not achievable:
1 = When HD link established in 100B-TX MII outputs are isolated
0 = Normal MII outputs operation
2 RXERR During IDLE 1, SWS, RW Detection of Receive Symbol Error During IDLE State:
1 = Enable detection of Receive symbol error during IDLE state
0 = Disable detection of Receive symbol error during IDLE state.
1 Odd-Nibble Detection Disable 0, SWS, RW Detection of Transmit Error:
1 = Disable detection of transmit error in odd-nibble boundary
0 = Enable detection of de-assertion of TX_EN on an odd-nibble boundary. In this case TX_EN is extended by one additional TX_CLK cycle and behaves as if TX_ER were asserted during that additional cycle.
0 RMII Receive Clock 0, SWS, RW RMII Receive Clock:
1 = RMII Data (RXD [1:0]) is sampled and referenced to RX_CLK
0 = RMII Data (RXD [1:0]) is sampled and referenced to XI

8.1.12 Software Strap Control Register 3 (SWSCR3)

This register contains the configuration bits used as strapping options or virtual strapping pins during HW RESET. These configuration values are programmed by the system processor after HW_RESET/POR, and then the “Config Done” - bit 15 of register SWSCR1 (0x0009) is set at the end of the configuration. An internal reset pulse is generated and the SW Strap bit values are latched into internal registers.

Table 8-15 SW Strap Control register 3 (SWSCR3), address 0x000B

BIT BIT NAME DEFAULT DESCRIPTION
15:11 RESERVED 0, RO RESERVED: Writes ignored, read as 0.
10 Fast Link Down Mode 0, RW Drop the link based on descrambler link loss, This option can be enabled in parallel to the other fast link down modes in bit [3:0]
1= Drop the link on descrambler link loss
0= Do not drop the link on descrambler link loss
9:7 RESERVED 0, RO RESERVED: Writes ignored, read as 0.
6 Polarity Swap 0, SWS, RW Polarity Swap:
1 = Inverted polarity on both pairs: TPTD+ ↔ TPTD-, TPRD+ ↔ TPRD-
0 = Normal polarity
Port Mirror function: To Enable port mirroring, set bit 5 and this bit high.
5 MDI/MDIX Swap 0, SWS, RW MDI/MDIX Swap:
1 = Swap MDI pairs (Receive on TPTD pair, Transmit on TPRD pair)
0 = MDI pairs normal (Receive on TPRD pair, Transmit on TPTD pair)
Port Mirror function: To Enable port mirroring, set this bit and bit 6 high.
4 Bypass 4B/5B 0, SWS, RW Bypass 4B/5B Encoder/Decoder Functionality:
1 = Bypass the 4B/5B Encoder in TX path and the Decoder in RX path to allow direct 5-bit TX and 5-bit RX interface to/from the MAC. In the TX path, the additional TXD [4] input pin is the TDI (pin 12) and in the RX path, the additional RXD [4] output pin is the RXERR (pin 41). Note: The PHY must be configured to operate in MII mode.
0 = Normal operation
3:0 Fast Link Down Mode 0, SWS, RW Fast Link Down Modes:
Bit 3 Drop the link based on RX Error count of the MII interface – When a predefined number of 32 RX Error occurrences in a 10µs interval is reached, the link will be dropped.
Bit 2 Drop the link based on MLT3 Errors count (Violation of the MLT3 coding in the DSP output) – When a predefined number of 20 MLT3 Error occurrences in a 10µs interval is reached, the link will be dropped.
Bit 1 Drop the link based on Low SNR Threshold – When a predefined number of 20 Threshold crossing occurrences in a 10µs interval is reached, the link will be dropped.
Bit 0 Drop the link based on Signal/Energy loss indication – When the Energy detector indicates Energy Loss, the link will be dropped. Typical reaction time is 10µs.
The Fast Link Down function is an OR of all these 5 options (bits 10, 3:0), so the designer can enable combinations of these conditions.

8.1.13 Extended Register Addressing

REGCR (0x000D) and ADDAR (0x000E) allow read/write access to the extended register set (addresses above 0x001F) using indirect addressing.

  • REGCR [15:14] = 00: A write to ADDAR modifies the extended register set address register. This address register must be initialized in order to access any of the registers within the extended register set.
  • REGCR [15:14] = 01: A read/write to ADDAR operates on the register within the extended register set selected (pointed to) by the value in the address register. The address register contents (pointer) remain unchanged.
  • REGCR [15:14] = 10: A read/write to ADDAR operates on the register within the extended register set selected (pointed to) by the value in the address register. After that access is complete, for both reads and writes, the value in the address register is incremented.
  • REGCR [15:14] = 11: A read/write to ADDAR operates on the register within the extended register set selected (pointed to) by the value in the address register. After that access is complete, for write accesses only, the value in the address register is incremented. For read accesses, the value of the address register remains unchanged.

8.1.13.1 Register Control Register (REGCR)

This register is the MDIO Manageable MMD access control. In general, register REGCR (4:0) is the device address DEVAD that directs any accesses of the ADDAR (0x000E) register to the appropriate MMD. REGCR also contains selection bits for auto increment of the data register. This register contains the device address to be written to access the extended registers. Write 0x1F into bits 4:0 of this register. REGCR also contains selection bits (15:14) for the address auto-increment mode of ADDAR.

Table 8-16 Register Control Register (REGCR), address 0x000D

BIT BIT NAME DEFAULT DESCRIPTION
15:14 Function 0, RW 00 = Address
01 = Data, no post increment
10 = Data, post increment on read and write
11 = Data, post increment on write only
13:5 RESERVED 0, RO RESERVED: Writes ignored, read as 0.
4:0 DEVAD 0, RW Device Address: In general, these bits [4:0] are the device address DEVAD that directs any accesses of ADDAR register (0x000E) to the appropriate MMD. Specifically, the TLK111 uses the vendor specific DEVAD [4:0] = “11111” for accesses. All accesses through registers REGCR and ADDAR should use this DEVAD. Transactions with other DEVAD are ignored.

8.1.13.2 Address or Data Register (ADDAR)

This register is the address/data MMD register. ADDAR is used in conjunction with REGCR register (0x000D) to provide the access by indirect read/write mechanism to the extended register set.

Table 8-17 Data Register (ADDAR), address 0x000E

BIT BIT NAME DEFAULT DESCRIPTION
15:0 Addr/data 0, RW If REGCR register 15:14 = 00, holds the MMD DEVAD's address register, otherwise holds the MMD DEVAD's data register

8.1.14 Fast Link Down Status Register

Table 8-18 Fast Link Down Status (FLDS), address 0x000F

BIT BIT NAME DEFAULT DESCRIPTION
15:9 RESERVED 0, RO RESERVED
8:4 Fast Link Down Status[4:0] 0, RO, LH Status Registers that latch high each time a given Fast Link Down mode is activated and causes a link drop (assuming this criterion was enabled):
Bit 4 Descrambler Loss Sync
Bit 3 RX Errors
Bit 2 MLT3 Errors
Bit 1 SNR level
Bit 0 Signal/Energy Lost
3:0 RESERVED 0, RO RESERVED

8.1.15 PHY Status Register (PHYSTS)

This register provides quick access to commonly accessed PHY control status and general information.

Table 8-19 PHY Status Register (PHYSTS), address 0x0010

BIT NAME DEFAULT DESCRIPTION
15 RESERVED 0, RO RESERVED: Writes ignored, read as 0.
14 MDI-X Mode 0,RO MDI-X mode as reported by the Auto-Negotiation state machine:
1 = MDI pairs swapped (Receive on TPTD pair, Transmit on TPRD pair)
0 = MDI pairs normal (Receive on TRD pair, Transmit on TPTD pair)
This bit will be affected by the settings of the AMDIX_EN and FORCE_MDIX bits in the PHYCR register. When MDIX is enabled, but not forced, this bit will update dynamically as the Auto-MDIX algorithm swaps between MDI and MDI-X configurations.
13 Receive Error Latch 0,RO/LH Receive Error Latch:
1 = Receive error event has occurred since last read of RXERCNT register (0x0015)
0 = No receive error event has occurred
This bit will be cleared upon a read of the RECR register
12 Polarity Status 0,RO Polarity Status:
1 = Inverted Polarity detected
0 = Correct Polarity detected
This bit is a duplication of bit 4 in the 10BTSCR register (0x001A). This bit will be cleared upon a read of the 10BTSCR register, but not upon a read of the PHYSTS register.
11 False Carrier Sense Latch 0,RO/LH False Carrier Sense Latch:
1 = False Carrier event has occurred since last read of FCSCR register (0x0014)
0 = No False Carrier event has occurred
This bit will be cleared upon a read of the FCSR register.
10 Signal Detect 0,RO/LL Signal Detect:
Active high 100Base-TX unconditional Signal Detect indication from PMD
9 Descrambler Lock 0,RO/LL Descrambler Lock:
Active high 100Base-TX Descrambler Lock indication from PMD
8 Page Received 0,RO Link Code Word Page Received:
1 = A new Link Code Word Page has been received. This bit is a duplicate of Page Received (bit 1) in the ANER register and it is cleared on read of the ANER register (0x0006).
0 = Link Code Word Page has not been received.
This bit will not be cleared upon a read of the PHYSTS register.
7 MII Interrupt 0,RO MII Interrupt Pending:
1 = Indicates that an internal interrupt is pending. Interrupt source can be determined by reading the MISR Register (0x0012). Reading the MISR will clear this Interrupt bit indication.
0 = No interrupt pending
6 Remote Fault 0,RO Remote Fault:
1 = Remote Fault condition detected. Fault criteria: notification from Link Partner of Remote Fault via Auto-Negotiation. Cleared on read of BMSR register (0x0001) or by reset.
0 = No remote fault condition detected
5 Jabber Detect 0,RO Jabber Detect:
1 = Jabber condition detected. This bit has meaning only in 10 Mb/s mode. This bit is a duplicate of the Jabber Detect bit in the BMSR register (0x0001).
0 = No Jabber
This bit will not be cleared upon a read of the PHYSTS register.
4 Auto-Neg Status 0,RO Auto-Negotiation Status:
1 = Auto-Negotiation complete
0 = Auto-Negotiation not complete
3 MII Loopback Status 0,RO MII Loopback:
1 = Loopback active (enabled)
0 = Normal operation
2 Duplex Status 0,RO Duplex Status:
1 = Full duplex mode
0 = Half duplex mode
This bit indicates duplex status and is determined from Auto-Negotiation or Forced Modes. Therefore, it is only valid if Auto-Negotiation is enabled and complete and there is a valid link or if Auto-Negotiation is disabled and there is a valid link.
1 Speed Status 0,RO Speed Status:
1 = 10 Mb/s mode
0 = 100 Mb/s mode
This bit indicates the status of the speed and is determined from Auto-Negotiation or Forced Modes. Speed Status is only valid if Auto-Negotiation is enabled and complete and there is a valid link or if Auto-Negotiation is disabled and there is a valid link.
0 Link Status 0,RO Link Status:
1 = Valid link established (for either 10 or 100 Mb/s operation). This bit is a duplicate of the Link Status bit in the BMSR register (0x0001).
0 = Link not established
This bit will not be cleared upon a read of the PHYSTS register.

8.1.16 PHY Specific Control Register (PHYSCR)

This register implements the PHY Specific Control register. This register allows access to general functionality inside the PHY to enable operation in reduced power modes and control interrupt mechanism.

Table 8-20 PHY Specific Control Register (PHYSCR), address 0x0011

BIT NAME DEFAULT DESCRIPTION
15 Disable PLL 0,RW Disable PLL:
1 = Disable internal clocks Circuitries
0 = Normal mode of operation
Note: Clock Circuitry can be disabled only in IEEE power-down mode
14 PS Enable 0,RW Power Save Modes Enable:
1 = Enable power save modes
0 = Normal mode of operation
13:12 PS Modes 00,RW Power Save Modes:
Power Mode Name Description
<00> Normal Normal operation mode. PHY is fully functional
<01> IEEE power down Low Power mode that shut down all internal circuitry beside SMI functionality.
<10> Active Sleep Low Power Active Energy Saving mode that shut down all internal circuitry beside SMI and energy detect functionalities. In this mode the PHY sends NLP every 1.4 Sec to wake up link-partner. Automatic power-up is done when link partner is detected.
<11> Passive Sleep Low Power Energy Saving mode that shut down all internal circuitry beside SMI and energy detect functionalities. Automatic power-up is done when link partner is detected.
11 Scrambler Bypass 0,RW Scrambler Bypass:
1 = Scrambler bypass enabled
0 = Scrambler bypass disabled
10 RESERVED 0, RO RESERVED: Writes ignored, read as 0.
9:8 Loopback FIFO Depth 01,RW Far-End Loopback FIFO Depth:
00 = 4 nibbles FIFO
01 = 5 nibbles FIFO
10 = 6 nibbles FIFO
11 = 8 nibbles FIFO
This FIFO is used to adjust RX (recovered) clock rate to TX clock rate. FIFO depth need to be set based on expected maximum packet size and clock accuracy. Default value sets to 5 nibbles.
7:5 RESERVED 000, RO RESERVED: Writes ignored, read as 0.
4 COL FD Enable 0, RW Collision in Full-Duplex Mode:
1 = Enable generating Collision signaling in Full Duplex
0 = Disable Collision indication in Full Duplex mode. Collision will be active in Half Duplex only.
3 INT POL 1,RW Interrupt Polarity:
1 = Steady state (normal operation) is 1 logic and during interrupt is 0 logic.
0 = Steady state (normal operation) is 0 logic and during interrupt is 1 logic.
2 tint 0,RW Test Interrupt:
1 = Generate an interrupt
0 = Do not generate interrupt
Forces the PHY to generate an interrupt to facilitate interrupt testing. Interrupts will continue to be generated as long as this bit remains set.
1 INT_EN 0,RW Interrupt Enable:
1 = Enable event based interrupts
0 = Disable event based interrupts
Enable interrupt dependent on the event enables in the MISR register (0x0012).
0 INT_OE 0,RW Interrupt Output Enable:
1 = INT / PWDN is an Interrupt Output
0 = INT / PWDN is a Power Down
Enable active low interrupt events via the INT / PWDN pin by configuring the INT / PWDN pin as an output.

8.1.17 MII Interrupt Status Register 1 (MISR1)

This register contains events status and enables for the interrupt function. If an event has occurred since the last read of this register, the corresponding status bit will be set. If the corresponding enable bit in the register is set, an interrupt will be generated if the event occurs. The PHYSCR register (0x0011) bits 1 and 0 must also be set to allow interrupts. The status indications in this register will be set even if the interrupt is not enabled.

Table 8-21 MII Interrupt Status Register 1 (MISR1), address 0x0012

BIT NAME DEFAULT DESCRIPTION
15:14 RESERVED 00, RO RESERVED: Writes ignored, read as 0.
13 Link Status Changed INT 0,RO, COR Change of Link Status interrupt:
1 = Change of link status interrupt is pending
0 = No change of link status
12 Speed Changed INT 0,RO, COR Change of Speed Status interrupt:
1 = Change of speed status interrupt is pending
0 = No change of speed status
11 Duplex Mode Changed INT 0,RO, COR Change of duplex status interrupt:
1 = Duplex status change interrupt is pending
0 = No change of duplex status
10 Auto-Negotiation Completed INT 0,RO, COR Auto-Negotiation Complete interrupt:
1 = Auto-negotiation complete interrupt is pending.
0 = No Auto-negotiation complete event is pending
9 FC HF INT 0,RO, COR False Carrier Counter half-full interrupt:
1 = False carrier counter (Register FCSCR, address 0x0014) exceeds half-full interrupt is pending
0 = False carrier counter half-full event is not pending
8 RE HF INT 0,RO, COR Receive Error Counter half-full interrupt:
1 = Receive error counter (Register RECR, address 0x0015) exceeds half full interrupt is pending
0 = No Receive error counter half full event pending
7:6 RESERVED 00, RO RESERVED: Writes ignored, read as 0.
5 Link Status Changed EN 0, RW Enable Interrupt on change of link status
4 Speed Changed EN 0, RW Enable Interrupt on change of speed status
3 Duplex Mode Changed EN 0, RW Enable Interrupt on change of duplex status
2 Auto-Negotiation Completed EN 0, RW Enable Interrupt on Auto-negotiation complete event
1 FC HF EN 0, RW Enable Interrupt on False Carrier Counter Register half-full event
0 RE HF EN 0, RW Enable Interrupt on Receive Error Counter Register half-full event

8.1.18 MII Interrupt Status Register 2 (MISR2)

This register contains events status and enables for the interrupt function. If an event has occurred since the last read of this register, the corresponding status bit will be set. If the corresponding enable bit in the register is set, an interrupt will be generated if the event occurs. The PHYSCR register (0x0011) bits 1 and 0 must also be set to allow interrupts. The status indications in this register will be set even if the interrupt is not enabled.

Table 8-22 MII Interrupt Status Register 2 (MISR2), address 0x0013

BIT NAME DEFAULT DESCRIPTION
15 RESERVED 0, RO RESERVED: Writes ignored, read as 0.
14 AN Error INT 0,RO, COR Auto-Negotiation Error Interrupt:
1 = Auto-negotiation error interrupt is pending
0 = No Auto-negotiation error event pending
13 Page Rec INT 0,RO, COR Page Receive Interrupt:
1 = Page has been received
0 = Page has not been received
12 Loopback FIFO OF/UF INT 0,RO, COR Loopback FIFO Overflow/Underflow Event Interrupt:
1 = FIFO Overflow/Underflow event interrupt pending
0 = No FIFO Overflow/Underflow event pending
11 MDI Crossover Changed INT 0,RO, COR MDI/MDIX Crossover Status Changed Interrupt:
1 = MDI crossover status changed interrupt is pending
0 = MDI crossover status has not changed
10 Sleep Mode INT 0,RO, COR Sleep Mode Event Interrupt:
1 = Sleep Mode event interrupt is pending
0 = No sleep mode event pending
9 Polarity Changed INT 0,RO, COR Polarity Changed Interrupt:
1 = Data polarity changed interrupt pending
0 = No Data polarity event pending
8 Jabber Detect INT 0,RO Jabber Detect Event Interrupt:
1 = Jabber detect event interrupt pending
0 = No Jabber detect event pending
7 RESERVED 0,RW RESERVED: Writes ignored, read as 0
6 AN Error EN 0,RW Enable Interrupt on Auto-Negotiation error event
5 Page Rec EN 0,RW Enable Interrupt on page receive event
4 Loopback FIFO OF/UF EN 0,RW Enable Interrupt on loopback FIFO overflow/underflow event
3 MDI Crossover Changed EN 0,RW Enable Interrupt on change of MDI/X status
2 Sleep Mode Event EN 0,RW Enable Interrupt sleep mode event
1 Polarity Changed EN 0,RW Enable Interrupt on change of polarity status
0 Jabber Detect EN 0,RW Enable Interrupt on Jabber detection event

8.1.19 False Carrier Sense Counter Register (FCSCR)

This counter provides information required to implement the "False Carriers" attribute within the MAU managed object class of Clause 30 of the IEEE 802.3u specification.

Table 8-23 False Carrier Sense Counter Register (FCSCR), address 0x0014

BIT NAME DEFAULT DESCRIPTION
15:8 RESERVED 0000 0000, RO RESERVED: Writes ignored, read as 0
7:0 FCSCNT 0,RO / COR False Carrier Event Counter:
This 8-bit counter increments on every false carrier event. This counter stops when it reaches its maximum count (FFh). When the counter exceeds half full (7Fh), an interrupt event is generated. This register is cleared on read.

8.1.20 Receiver Error Counter Register (RECR)

This counter provides information required to implement the "Symbol Error During Carrier" attribute within the PHY managed object class of Clause 30 of the IEEE 802.3u specification.

Table 8-24 Receiver Error Counter Register (RECR), address 0x0015

BIT BIT NAME DEFAULT DESCRIPTION
15:0 RX Error Count 0, RO, / COR RX_ER Counter:
When a valid carrier is present (only while RXDV is set), and there is at least one occurrence of an invalid data symbol, this 16-bit counter increments for each receive error detected. The RX_ER counter does not count in MII loopback mode. The counter stops when it reaches its maximum count of FFFFh. When the counter exceeds half-full (7FFFh), an interrupt is generated. This register is cleared on read.

8.1.21 BIST Control Register (BISCR)

This register is used for Build-In Self Test (BIST) configuration. The BIST functionality provides Pseudo Random Bit Stream (PRBS) mechanism including packet generation generator and checker. Selection of the exact loopback point in the signal chain is also done in this register.

Table 8-25 BIST Control Register (BISCR), address 0x0016

BIT NAME DEFAULT DESCRIPTION
15 RESERVED 0, RO RESERVED: Writes ignored, read as 0
14 PRBS Count Mode 0, RW PRBS Single/Continues Mode:
1 = Continuous mode, the PRBS counters reaches max count value, pulse is generated and counter starts counting from zero again.
0 = Single mode, When BIST Error Counter reaches its max value, PRBS checker stops counting.
13 Generate PRBS Packets 0, RW Generated PRBS Packets:
1 = When packet generator is enabled, generate continuous packets with PRBS data. When packet generator is disabled, PRBS checker is still enabled.
0 = When packet generator is enabled, generate single packet with constant data. PRBS gen/check is disabled.
12 Packet Generation Enable 0, RW Packet Generation Enable:
1 = Enable packet generation with PRBS data
0 = Disable packet generator
11 PRBS Checker Lock 0,RO PRBS Checker Lock Indication:
1 = PRBS checker is locked and synced on received bit stream
0 = PRBS checker is not locked
10 PRBS Checker Sync Loss 0,RO,LH PRBS Checker Sync Loss Indication:
1 = PRBS checker lose sync on received bit stream – This is an error indication
0 = PRBS checker is not locked
9 Packet Gen Status 0,RO Packet Generator Status Indication:
1 = Packet Generator is active and generate packets
0 = Packet Generator is off
8 Power Mode 0,RO Sleep Mode Indication:
1 = Indicate that the PHY is in normal power mode
0 = Indicate that the PHY is in one of the sleep modes, either active or passive
7 RESERVED 0, RO RESERVED: Writes ignored, read as 0.
6 Transmit in MII Loopback 0, RW Transmit Data in MII Loop-back Mode (valid only at 100BT):
1 = Enable transmission of the data from the MAC received on the TX pins to the line in parallel to the MII loopback to RX pins. This bit may be set only in MII Loopback mode – setting bit 14 in BMCR register (0x0000).
0 = Data is not transmitted to the line in MII loopback
5 RESERVED 0, RO RESERVED: Must be 0
4:0 Loopback Mode 0, RW Loop-back Mode Select:
The PHY provides several options for Loopback that test and verify various functional blocks within the PHY. Enabling loopback mode allows in-circuit testing of the TLK111 digital and analog data path
Near-end Loopback
00001 = PCS Input Loopback
00010 = PCS Output Loopback
00100 = Digital Loopback
01000 = Analog Loopback (requires 100Ω termination)
Far-end Loopback:
10000 = Reverse Loopback

8.1.22 RMII Control and Status Register (RCSR)

This register configures the RMII Mode of operation. When RMII mode is disabled, the RMII functionality is bypassed.

Table 8-26 RMII Control and Status Register (RCSR), address 0x0017

BIT NAME DEFAULT DESCRIPTION
15:6 RESERVED 0000 0000 00, RO RESERVED: Writes ignored, read as 0.
5 RMII Mode 0, RW, Pin_Strap RMII Mode Enable:RMII Mode is operational if device powered up in RMII mode (pin_strap) and 50Mhz clock present. Please note, that in order to switch from RMII to MII and vise versa, the PHY must initialize after power up in RMII mode (Strap is '1' and REF_CLK is 50MHz). If the PHY initializes in MII mode, this bit has no effect.
1 = Enable RMII (Reduced MII) mode of operation
0 = Enable MII mode of operation
4 RMII Revision Select 0, RW RMII Revision Select:
1 = (RMII revision 1.0) CRS_DV will remain asserted until final data is transferred. CRS_DV will not toggle at the end of a packet.
0 = (RMII revision 1.2) CRS_DV will toggle at the end of a packet to indicate de-assertion of CRS.
3 RMII OVFL Status 0, COR RX FIFO Over Flow Status:
1 = Normal
0 = Overflow detected
2 RMII OVFL Status 0, COR RX FIFO Under Flow Status:
1 = Normal
0 = Underflow detected
1:0 ELAST_BUF 01, RW Receive Elasticity Buffer Size:
This field controls the Receive Elasticity Buffer which allows for frequency variation tolerance between the 50MHz RMII clock and the recovered data. The following values indicate the tolerance in bits for a single packet. The minimum setting allows for standard Ethernet frame sizes at ±50ppm accuracy for both RMII and Receive clocks. For greater frequency tolerance the packet lengths may be scaled (for ±100ppm, divide the packet lengths by 2).
00 = 14 bit tolerance (up to 16800 byte packets)
01 = 2 bit tolerance (up to 2400 byte packets)
10 = 6 bit tolerance (up to 7200 byte packets)
11 = 10 bit tolerance (up to 12000 byte packets)

8.1.23 LED Control Register (LEDCR)

This register provides the ability to directly manually control any or all LED outputs .

Table 8-27 LED Control Register (LEDCR), address 0x0018

BIT NAME DEFAULT DESCRIPTION
15:11 RESERVED 0000 0, ro RESERVED: Writes ignored, read as 0.
10:9 Blink Rate 10, RW LED Blinking Rate (ON/OFF duration):
00 = 20Hz (50mSec)
01 = 10Hz (100mSec)
10 = 5Hz (200mSec)
11 = 2Hz (500mSec)
8 LED Speed Polarity 0, RW, Pin_Strap LED Speed Polarity Setting:
1 = Active High polarity setting
0 = Active Low polarity setting
Speed LED’s polarity defined by strapping value of this pin. This register allows override of this strapping value.
7 LED Link Polarity 0, RW, Pin_Strap LED Link Polarity Setting:
1 = Active High polarity setting
0 = Active Low polarity setting
Link LED polarity defined by strapping value of this pin. This register allows override of this strapping value.
6 LED Active Polarity 0, RW, Pin_Strap LED Activity Polarity Setting:
1 = Active High polarity setting
0 = Active Low polarity setting
Activity LED’s polarity defined by strapping value of this pin. This register allows override of this strapping value.
5 Drive Speed LED 0,RW Drive LED Speed to the forced On/Off setting defined in bit 2:
1 = Drive value of On/Off bit onto LED_SPEED output pin
0 = Normal operation
4 Drive Link LED 0, RW Drive LED Link to the forced On/Off setting defined in bit 1:
1 = Drive value of On/Off bit onto LED_LINK output pin
0 = Normal operation
3 Drive Active LED 0,RW Drive LED Activity to the forced On/Off setting defined in bit 0:
1 = Drive value of On/Off bit onto LED_ACT output pin
0 = Normal operation
2 Speed LED On/Off Setting 0, RW Value to force on Speed LED output
1 Link LED On/Off Setting 0, RW Value to force on Link LED output
0 Act LED On/Off Setting 0, RW Value to force on Activity LED output

8.1.24 PHY Control Register (PHYCR)

This register provides the ability to control and set general functionality inside the PHY.

Table 8-28 PHY Control Register (PHYCR), address 0x0019

BIT NAME DEFAULT DESCRIPTION
15 Auto MDI/X Enable 1, RW, Pin_Strap Auto-MDIX Enable:
1 = Enable Auto-negotiation Auto-MDIX capability
0 = Disable Auto- negotiation Auto-MDIX capability
14 Force MDI/X 0, RW Force MDIX:
1 = Force MDI pairs to cross. (Receive on TPTD pair, Transmit on TPRD pair)
0 = Normal operation. (Transmit on TPTD pair, Receive on TPRD pair)
13 Pause RX Status 0, RO Pause Receive Negotiated Status: Indicates that pause receive should be enabled in the MAC. Based on bits [11:10] in ANAR register and bits [11:10] in ANLPAR register settings.
This function shall be enabled according to IEEE 802.3 Annex 28B Table 28B-3, “Pause Resolution”, only if the Auto-Negotiated Highest Common Denominator is a full duplex technology.
12 Pause TX Status 0,RO Pause Transmit Negotiated Status:
Indicates that pause transmit should be enabled in the MAC. Based on bits [11:10] in ANAR register and bits [11:10] in ANLPAR register settings.
This function shall be enabled according to IEEE 802.3 Annex 28B Table 28B-3, “Pause Resolution”, only if the Auto-Negotiated Highest Common Denominator is a full duplex technology.
11 MI Link Status 0, RO MII Link Status:
1 = 100BT Full-duplex Link is active and it was established using Auto-Negotiation
0 = No active link of 100BT Full-duplex, established using Auto-Negotiation
10:8 RESERVED 000, RO RESERVED: Writes ignored, read as 0.
7 Bypass LED Stretching 0, RW Bypass LED Stretching:
1 = Bypass LED stretching
0 = Normal LED operation
Set this bit to 1 to bypass the LED stretching; the LEDs reflect the internal value.
6:5 LED CFG 0, RW
0, RW, Pin_Strap, SWSC_Strap		 LED Configuration Modes:
Mode LED_CFG[1] LED_CFG[0] LED_LINK LED_SPEED LED_ACT
1 Don't Care 1 ON for Good Link
OFF for No Link 		ON in 100 Mb/s
OFF in 10 Mb/s		 ON Pulse for Activity
OFF for No Activity
2 0 0 ON for Good Link
BLINK for Activity 		ON for Collision
OFF for No Collision
3 1 0 ON for Full Duplex
OFF for Half Duplex
4:0 PHY ADDR 0000 1, RO PHY Address:
Strapping configuration for PHY Address.

8.1.25 10Base-T Status/Control Register (10BTSCR)

This register provides the ability to control and read status of the PHY’s internal 10Base-T functionality.

Table 8-29 10Base-T Status/Control Register (10BTSCR), address 0x001A

BIT NAME DEFAULT DESCRIPTION
15:14 RESERVED 000, RO RESERVED: Writes ignored, read as 0.
13 Receiver TH 0, RW Lower Receiver Threshold Enable:
1 = Enable 10Base-T lower receiver threshold to allow operation with longer cables
0 = Normal 10Base-T operation
12:9 Squelch 0000, RW Squelch Configuration:
Used to set the Peak Squelch ‘ON’ threshold for the 10Base-T receiver. Every step is equal to 50mV and allow raising/lowering the Squelch threshold from 200mV to 600mV. The default Squelch threshold is set to 200mV.
8 RESERVED 0, RO RESERVED: Writes ignored, read as 0.
7 NLP Disable 0, RW NLP Transmission Control:
1 = Disable transmission of NLPs
0 = Enable transmission of NLPs
6:5 RESERVED 00, RO RESERVED: Writes ignored, read as 0.
4 Polarity Status 0, RO 10Mb Polarity Status:
1 = Inverted Polarity detected
0 = Correct Polarity detected
This bit is a duplication of bit 12 in the PHYSTS register (0x0010). Both bits will be cleared upon a read of 10BTSCR register, but not upon a read of the PHYSTS register.
3:1 RESERVED 000, RO RESERVED: Writes ignored, read as 0.
0 Jabber Disable 0, RW Jabber Disable:
1 = Jabber function disabled
0 = Jabber function enabled
Note: This function is applicable only in 10Base-T

8.1.26 BIST Control and Status Register 1 (BICSR1)

This register provides the total number of error bytes that was received by the PRBS checker and defines the Inter packet Gap (IPG) for the packet generator.

Table 8-30 BIST Control and Status Register 1 (BICSR1), address 0x001B

BIT BIT NAME DEFAULT DESCRIPTION
15:8 BIST Error Count 0, RO BIST Error Count:
Holds number of erroneous bytes that were received by the PRBS checker. Value in this register is locked when write is done to bit[0] or bit[1] (see below).
When PRBS Count Mode set to zero, count stops on 0xFF. See BISCR register (0x0016) for further details
Note: Writing “1” to bit 15 will lock counter’s value for successive read operation and clear the BIST Error Counter.
7:0 BIST IPG Length 0111 1101, RW BIST IPG Length:
Inter Packet Gap (IPG) Length defines the size of the gap (in bytes) between any 2 successive packets generated by the BIST. Default value is 0x7D which is equal to 125 bytes

8.1.27 BIST Control and Status Register2 (BICSR2)

This register allows programming the length of the generated packets in bytes for the BIST mechanism.

Table 8-31 BIST Control and Status Register 2 (BICSR2), address 0x001C

BIT BIT NAME DEFAULT DESCRIPTION
15:11 RESERVED 0000 0, RO RESERVED: Writes ignored, read as 0.
10:0 BIST Packet Length 101 1101 1100, RW BIST Packet Length:
Length of the generated BIST packets. The value of this register defines the size (in bytes) of every packet that generated by the BIST. Default value is 0x5DC which is equal to 1500 bytes

8.2 Cable Diagnostic Control Register (CDCR)

Cable Diagnostic Control Register (CDCR), address 0x001E

BIT NAME DEFAULT FUNCTION
15 Diagnostic Start 0, RW Cable Diagnostic Process Start:
1 = Start execute cable measurement
0 = Cable Diagnostic is disabled
Diagnostic Start bit is cleared with raise of Diagnostic Done indication.
14:10 RESERVED 000 00, RO RESERVED: Writes ignored, read as 0.
9:8 Link Quality 00, RO Link Quality Indication
00 = Reserved
01 = Good Quality Link Indication
10 = Mid Quality Link Indication
11 = Poor Quality Link Indication
The value of these bits are valid only when link is active – While reading “1” from “Link Status” bit 0 on PHYSTS register (0x0010).
7:4 RESERVED 0000, RO RESERVED: Writes ignored, read as 0.
3:2 RESERVED 00, RO RESERVED: Writes ignored, read as 0.
1 Diagnostic Done 0, RO Cable Diagnostic Process Done:
1 = Indication that cable measurement process completed
0 = Diagnostic has not completed
0 Diagnostic Fail 0, RO Cable Diagnostic Process Fail:
1 = Indication that cable measurement process failed
0 = Diagnostic has not failed

8.3 PHY Reset Control Register (PHYRCR)

Table 8-32 PHY Reset Control Register (PHYRCR), address 0x001F

BIT NAME DEFAULT FUNCTION
15 Software Reset 0, RW,SC Software Reset:
1 = Reset PHY. This bit is self cleared and has same effect as Hardware reset pin.
0 = Normal Operation
14 Software Restart 0, RW,SC Software Restart:
1 = Reset PHY. This bit is self cleared and resets all PHY circuitry except the registers.
0 = Normal Operation
13:0 RESERVED 00 0000 0000 0000, RO
Writes ignored, read as 0

8.4 Multi LED Control register (MLEDCR)

Table 8-33 Multi LED Control register (MLEDCR), address 0x0025

BIT NAME DEFAULT FUNCTION
15:11 RESERVED 0000 0, RO Writes ignored, read as 0
10 MLED pin 42 Route & Enable (COL Disable) 0, RW Disable collision pin, and enable and route MLED (Multi LED) output to pin 42
Default - LINK advertise, LED_CFG strap can change to LINK+ACT
9 MLED Polarity RW Strap RW, Strap The polarity of MLED depends on the routing configuration and the strap in use on the selected pin. If the pin is (strap) PU then polarity is low, if the pin is (strap) PD then polarity is high.
8:7 RESERVED 0 0, RW, SC RESERVED
6:3 MLED Configuration 000 0, RW 0000 = Link OK
0001 = RX/TX Activity
0010 = TX Activity
0011 = RX Activity
0100 = Collision
0101 = Speed: High for 100 Base TX
0110 = Speed: High for 10 Base TX
0111 = Full Duplex
1000 = Link OK / Blink on TX/RX Activity
1001 = Active Stretch Signal
1010 = MII LINK (100BT+FD)
2:1 MLED pin Routing Config 00, RW Select between 3 current LEDs, only when 'MLED pin Routing Enable' bit is enabled
00 - LED LINK
01 - LED SPEED
10 - LED ACT
11 - LED LINK (Like DFLT)
0 MLED pin Routing enable 0, RW Enable routing for MLED according to MLED pin routing config

8.5 IEEE1588 Precision Timing Pin Select (PTPPSEL)

This register configures the .

Table 8-34 IEEE1588 Precision Timing Pin Select (PTPPSEL), address 0x003E

BIT BIT NAME DEFAULT DESCRIPTION
15:7 RESERVED <0000 0>, RO RESERVED: Writes ignored, read as 0.
6:4 cfg_1588_TX_pin_sel 0, RW IEEE 1588 TX Pin Select: Assigns transmit SFD pulse indication to pin selected by value in column at right. 001 - LED_ACT Pin
010 - LED_SPEED Pin
011 - LED_LINK Pin
100- CRS Pin
101 - COL Pin
110 - PWDNN/INT Pin
111 - No pulse output
3 RESERVED 0, RO RESERVED: Writes ignored, read as 0.
2:0 cfg_1588_RX_pin_sel 0, RW IEEE 1588 RX Pin Select: Assigns receive SFD pulse indication to pin selected by value in column at right.

8.6 IEEE1588 Precision Timing Configuration (PTPCFG)

This register allows programming the length of the generated packets in bytes for the BIST mechanism.

Table 8-35 IEEE1588 Precision Timing Configuration (PTPCFG), address 0x003F

BIT BIT NAME DEFAULT DESCRIPTION
15:13 cfg_1588_TX_set_phase <101>, RW PTP Transmit Timing: Set 1588 indication for TX path (8ns step)
12:10 cfg_1588_RX_set_phase <101>, RW PTP Receive TIming: Set 1588 indication for RX path (8ns step)
9:8 cfg_TX_ERR_sel 0, (TRIM) Configure TX ERR Input Pin:
00 - No TX ERR
01 - Use LED ACT as TX_ERR
10 - Use PWRDN as TX_ERR
11 - USe COL as TX_ERR
7:0 RESERVED <0100 0100>, RW RESERVED

8.7 TX_CLK Phase Shift Register (TXCPSR)

This register allows programming the phase of the MII transmit clock (TX_CLK pin). The TX_CLK has a fixed phase to the XI pin. However the default phase, while fixed, may not be ideal for all systems, therefore this register may be used by the system to align the reference clock (XI pin) to the TX_CLK. The phase shift value is in 4ns units. The phase shift value should be between 0 and 10 (0ns to 40ns). If value greater than 10 is written, the update value will be the written value modulo 10.

Table 8-36 TX_CLK Phase Shift Register (TXCPSR), address 0x0042

BIT NAME DEFAULT FUNCTION
15:5 RESERVED 0000 0000 000, RO RESERVED: Writes ignored, read as 0
4 Phase Shift Enable 0,RW,SC TX Clock Phase Shift Enable:
1 = Perform Phase Shift to the TX_CLK according to the value written to Phase Shift Value in bits [4:0].
0 = No change in TX Clock phase
3:0 Phase Shift Value 0000,RW TX Clock Phase Shift Value:
The value of this register represents the current phase shift between Reference clock at XI and MII Transmit Clock at TX_CLK. Any different value that will be written to these bits will shift TX_CLK by 4 times the difference (in nSec).
For example, if the value of this register is 0x2, Writing 0x9 to this register shifts TX_CLK by 28nS (4 times 7).However, since the maximum difference between XI and TX_CLK could be 40nSec (value of 10) in case of writing value bigger than 10, the updated value is the written value modulo 10.

8.8 Power Back Off Control Register (PWRBOCR)

Table 8-37 Power Back Off Control Register (PWRBOCR), address 0x00AE

BIT NAME DEFAULT FUNCTION
15 RESERVED 1, RO RESERVED
14 RESERVED 0, RO RESERVED
13:9 RESERVED 00 000, RO RESERVED
8:6 Power Back Off 0, RW Power Back Off Level: See Application Note SLLA328
000 = Normal Operation
001 = Level 1 (up to 5m cable between TLK link partners)
010 = Level 2 (up to 80m cable between TLK link partners)
011 = Level 3 (up to 100m cable between TLK link partners)
Others = Reserved
5:0 RESERVED 10 0000, RO RESERVED

8.9 Voltage Regulator Control Register (VRCR)

This register gives the host processor the ability to power down the voltage-regulator block of the PHY via register access. This power-down operation is available in systems operating with an external power supply.

Table 8-38 Voltage Regulator Control Register (VRCR), address 0x00D0

BIT NAME DEFAULT FUNCTION
15 VRPD 0, RW, SC Voltage Regulator Power Down:
1 = Power Down. Allow the system to power down the voltage regulator block of the PHY using register access.
0 = Normal Operation. Voltage Regulator is powered and outputs voltage on the PFBOUT pin.
14:4 RESERVED 000 0000 0000, RW RESERVED: Must be written as 0.
3:0 VR Control 0000, RW Voltage Regulator Control This value should be ignored on read. To write to this register, perform a read followed by a write with the desired value.

8.10 Cable Diagnostic Configuration/Result Registers

8.10.1 ALCD Control and Results 1 (ALCDRR1)

Table 8-39 ALCD Control and Results 1 (ALCDRR1), address 0x0155

BIT BIT NAME DEFAULT DESCRIPTION
15 alcd_start 0, SC 1 = Start ALCD
14:13 00, RO RESERVED: Writes ignored, read as 0.
12 alcd_done 0, RO TPTD Diagnostic Bypass
1 = Bypass TPTD diagnostic. TDR on TPTD pair is not executed.
0 = TDR is executed on TPTD pair
11:4 alcd_out1 0000 0000, RO alcd_out1
3 RESERVED 0, RO RESERVED: Writes ignored, read as 0
2:0 alcd_ctrl 001,RW Control of ALCD Average factor

8.10.2 Cable Diagnostic Specific Control Registers (CDSCR1 - CDSCR4)

Use CDSCR1 to select the channel for the cable diagnostics test. CDSCR1 contains the enable and bypass bits for the diagnostic tests, and defines the number of executed and averaged TDR sequences. CDSCR2 - CDSCR4 configure other parameters for cable diagnostics.

Table 8-40 Cable Diagnostic Specific Control Register (CDSCR), address 0x0170

BIT BIT NAME DEFAULT DESCRIPTION
15 RESERVED 0, RO RESERVED: Writes ignored, read as 0.
14 Diagnostic Cross Disable 0, RW Cross TDR Diagnostic mode
1 = Disable TDR Cross mode – TDR will be executed in regular mode only
0 = Diagnostic of crossing pairs is enabled In Cross Diagnostic mode, the TDR mechanism is looking for reflection on the other pair to check short between pairs.
13 Diagnostic TPTD Bypass 0, RW TPTD Diagnostic Bypass
1 = Bypass TPTD diagnostic. TDR on TPTD pair will not be executed.
0 = TDR is executed on TPTD pair
In bypass TPTD, results are available in TPRD slots.
12 Diagnostic TPRD Bypass 0, RO TPRD Diagnostic Bypass
1 = Bypass TPRD diagnostic. TDR on TPRD pair will not be executed.
0 = TDR is executed on TPRD pair
11 RESERVED 1, RW RESERVED: Must be Set to 1.
10:8 Diagnostics Average Cycles 110, RW Number Of TDR Cycles to Average:
<000>: 1 TDR cycle
<001>: 2 TDR cycles
<010>: 4 TDR cycles
<011>: 8 TDR cycles
<100>: 16 TDR cycles
<101>: 32 TDR cycles
<110>: 64 TDR cycles (default)
<111>: Reserved
7:0 RESERVED 0, RO RESERVED: Writes ignored, read as 0.

Table 8-41 Cable Diagnostic Specific Control Register 2 (CDSCR2), address 0x0171

BIT BIT NAME DEFAULT DESCRIPTION
15:4 RESERVED 1100 1000 0101, RW RESERVED: Ignore on read
3:0 TDR pulse control 1100, RW Configure expected self reflection in TDR

Table 8-42 Cable Diagnostic Specific Control Register 3 (CDSCR3), address 0x0173

BIT BIT NAME DEFAULT DESCRIPTION
15:8 Cable length cfg 1111 1111, RW Configure duration of listening to detect long cable reflections
7:0 RESERVED 1111 1111, RW RESERVED: Ignore on read

Table 8-43 Cable Diagnostic Specific Control Register 4 (CDSCR4), address 0x0177

BIT BIT NAME DEFAULT DESCRIPTION
15:13 RESERVED 000, RW RESERVED: Ignore on read
12:8 Short cables TH 1 1000, RW TH to compensate for strong reflections in short cables
7:0 RESERVED 1001 0110, RW RESERVED: Ignore on read

8.10.3 Cable Diagnostic Location Results Register 1 (CDLRR1)

This register provides the peaks locations after execution of the TDR. The values of this register are valid after reading 1 in Diagnostic Done bit 1 in register CDCR (0x1E).

Table 8-44 Cable Diagnostic Location Results Register 1 (CDLRR1), address 0x0180

BIT NAME DEFAULT FUNCTION
15:8 TPTD Peak Location 2 0000 0000, RO Location of the Second peak discovered by the TDR mechanism on Transmit Channel (TPTD). The value of these bits is translated into distance from the PHY
7:0 TPTD Peak Location 1 0000 0000, RO Location of the First peak discovered by the TDR mechanism on Transmit Channel (TPTD). The value of these bits is translated into distance from the PHY

8.10.4 Cable Diagnostic Location Results Register 2 (CDLRR2)

This register provides the peaks locations after execution of the TDR. The values of this register are valid after reading 1 in Diagnostic Done bit 1 in register CDCR (0x1E).

Table 8-45 Cable Diagnostic Location Results Register 2 (CDLRR2), address 0x0181

BIT NAME DEFAULT FUNCTION
15:8 TPTD Peak Location 4 0000 0000, RO Location of the Fourth peak discovered by the TDR mechanism on Transmit Channel (TPTD). The value of these bits is translated into distance from the PHY.
7:0 TPTD Peak Location 3 0000 0000, RO Location of the Third peak discovered by the TDR mechanism on Transmit Channel (TPTD). The value of these bits is translated into distance from the PHY.

8.10.5 Cable Diagnostic Location Results Register 3 (DDLRR3)

This register provides the peaks locations after execution of the TDR. The values of this register are valid after reading 1 in Diagnostic Done bit 1 in register CDCR (0x1E).

Table 8-46 Cable Diagnostic Location Results Register 3 (DDLRR3), address 0x0182

BIT NAME DEFAULT FUNCTION
15:8 TPRD Peak Location 1 0000 0000, RO Location of the First peak discovered by the TDR mechanism on Receive Channel (TPRD). The value of these bits is translated into distance from the PHY.
7:0 TPTD Peak Location 5 0000 0000, RO Location of the Fifth peak discovered by the TDR mechanism on Transmit Channel (TPTD). The value of these bits is translated into distance from the PHY.

8.10.6 Cable Diagnostic Location Results Register 4 (CDLRR4)

This register provides the peaks locations after execution of the TDR. The values of this register are valid after reading 1 in Diagnostic Done bit 1 in register CDCR (0x1E).

Table 8-47 Cable Diagnostic Location Results Register 4 (CDLRR4), address 0x0183

BIT NAME DEFAULT FUNCTION
15:8 TPRD Peak Location 3 0000 0000, RO Location of the Third peak discovered by the TDR mechanism on Receive Channel (TPRD). The value of these bits is translated into distance from the PHY.
7:0 TPRD Peak Location 2 0000 0000, RO Location of the Second peak discovered by the TDR mechanism on Receive Channel (TPRD). The value of these bits is translated into distance from the PHY.

8.10.7 Cable Diagnostic Location Results Register 5 (CDLRR5)

This register provides the peaks locations after execution of the TDR. The values of this register are valid after reading 1 in Diagnostic Done bit 1 in register CDCR (0x1E).

Table 8-48 Cable Diagnostic Location Results Register 5 (CDLRR5), address 0x0184

BIT NAME DEFAULT FUNCTION
15:8 TPRD Peak Location 5 0000 0000, RO Location of the Fifth peak discovered by the TDR mechanism on Receive Channel (TPRD). The value of these bits is translated into distance from the PHY.
7:0 TPRD Peak Location 4 0000 0000, RO Location of the Fourth peak discovered by the TDR mechanism on Receive Channel (TPRD). The value of these bits is translated into distance from the PHY.

8.10.8 Cable Diagnostic Amplitude Results Register 1 (CDARR1)

This register provides the peaks amplitude measurement after the execution of the TDR. The values of this register are valid after reading 1 in Diagnostic Done bit 1 in register CDCR (0x1E).

Table 8-49 Cable Diagnostic Amplitude Results Register 1 (CDARR1), address 0x0185

BIT NAME DEFAULT FUNCTION
15 RESERVED 0,RO RESERVED: Writes ignored, read as 0.
14:8 TPTD Peak Amplitude 2 000 0000, RO Amplitude of the Second peak discovered by the TDR mechanism on Transmit Channel (TPTD). The value of these bits is translated into type of cable fault and-or interference.
This amplitude value refers to peak location stored in bits [15:8] in register CDLRR1 (0x180)
7 RESERVED 0, RO RESERVED: Writes ignored, read as 0.
6:0 TPTD Peak Amplitude 1 000 0000, RO Amplitude of the First peak discovered by the TDR mechanism on Transmit Channel (TPTD). The value of these bits is translated into type of cable fault and-or interference.
This amplitude value refers to peak location stored in bits [7:0] in register CDLRR1 (0x180)

8.10.9 Cable Diagnostic Amplitude Results Register 2 (CDARR2)

This register provides the peaks amplitude measurement after the execution of the TDR. The values of this register are valid after reading 1 in Diagnostic Done bit 1 in register CDCR (0x1E).

Table 8-50 Cable Diagnostic Amplitude Results Register 2 (CDARR2), address 0x0186

BIT NAME DEFAULT FUNCTION
15 RESERVED 0,RO RESERVED: Writes ignored, read as 0.
14:8 TPTD Peak Amplitude 4 000 0000, RO Amplitude of the Fourth peak discovered by the TDR mechanism on Transmit Channel (TPTD). The value of these bits is translated into type of cable fault and-or interference.
This amplitude value refers to peak location stored in bits [15:8] in register CDLRR2 (0x181)
7 RESERVED 0, RO RESERVED: Writes ignored, read as 0.
6:0 TPTD Peak Amplitude 3 000 0000, RO Amplitude of the Third peak discovered by the TDR mechanism on Transmit Channel (TPTD). The value of these bits is translated into type of cable fault and-or interference.
This amplitude value refers to peak location stored in bits [7:0] in register CDLRR2 (0x181)

8.10.10 Cable Diagnostic Amplitude Results Register 3 (CDARR3)

This register provides the peaks amplitude measurement after the execution of the TDR. The values of this register are valid after reading 1 in Diagnostic Done bit 1 in register CDCR (0x1E).

Table 8-51 Cable Diagnostic Amplitude Results Register 3 (CDARR3), address 0x0187

BIT NAME DEFAULT FUNCTION
15 RESERVED 0, RO RESERVED: Writes ignored, read as 0.
14:8 TPRD Peak Amplitude 1 000 0000, RO Amplitude of the First peak discovered by the TDR mechanism on Receive Channel (TPRD). The value of these bits is translated into type of cable fault and-or interference.
This amplitude value refers to peak location stored in bits [15:8] in register CDLRR3 (0x182)
7 RESERVED 0, RO RESERVED: Writes ignored, read as 0.
6:0 TPTD Peak Amplitude 5 000 0000, RO Amplitude of the Fifth peak discovered by the TDR mechanism on Transmit Channel (TPTD). The value of these bits is translated into type of cable fault and-or interference.
This amplitude value refers to peak location stored in bits [7:0] in register CDLRR3 (0x182)

8.10.11 Cable Diagnostic Amplitude Results Register 4 (CDARR4)

This register provides the peaks amplitude measurement after the execution of the TDR. The values of this register are valid after reading 1 in Diagnostic Done bit 1 in register CDCR (0x1E).

Table 8-52 Cable Diagnostic Amplitude Results Register 4 (CDARR4), address 0x0188

BIT NAME DEFAULT FUNCTION
15 RESERVED 0, RO RESERVED: Writes ignored, read as 0.
14:8 TPRD Peak Amplitude 3 000 0000, RO Amplitude of the Third peak discovered by the TDR mechanism on Receive Channel (TPRD). The value of these bits is translated into type of cable fault and-or interference.
This amplitude value refers to peak location stored in bits [15:8] in register CDLRR4 (0x183)
7 RESERVED 0, RO RESERVED: Writes ignored, read as 0.
6:0 TPRD Peak Amplitude 2 000 0000, RO Amplitude of the Second peak discovered by the TDR mechanism on Receive Channel (TPRD). The value of these bits is translated into type of cable fault and-or interference.
This amplitude value refers to peak location stored in bits [7:0] in register CDLRR4 (0x183)

8.10.12 Cable Diagnostic Amplitude Results Register 5 (CDARR5)

This register provides the peaks amplitude measurement after the execution of the TDR. The values of this register are valid after reading 1 in Diagnostic Done bit 1 in register CDCR (0x1E).

Table 8-53 Cable Diagnostic Amplitude Results Register 5 (CDARR5), address 0x0189

BIT NAME DEFAULT FUNCTION
15 RESERVED 0, RO RESERVED: Writes ignored, read as 0.
14:8 TPRD Peak Amplitude 5 000 0000, RO Amplitude of the Fifth peak discovered by the TDR mechanism on Receive Channel (TPRD). The value of these bits is translated into type of cable fault and-or interference.
This amplitude value refers to peak location stored in bits [15:8] in register CDLRR4 (0x184)
7 RESERVED 0, RO RESERVED: Writes ignored, read as 0.
6:0 TPRD Peak Amplitude 4 000 0000, RO Amplitude of the Fourth peak discovered by the TDR mechanism on Receive Channel (TPRD). The value of these bits is translated into type of cable fault and-or interference.
This amplitude value refers to peak location stored in bits [7:0] in register CDLRR4 (0x184)

8.10.13 Cable Diagnostic General Results Register (CDGRR)

This register provides general measurement results after the execution of the TDR. The Cable Diagnostic software should post process this result together with other Peaks’ location and amplitude results.

Table 8-54 Cable Diagnostic General Results Register (CDGRR), address 0x018A

BIT NAME DEFAULT FUNCTION
15 TPTD Peak Polarity 5 0, RO Polarity of the Fifth peak discovered by the TDR mechanism on Transmit Channel (TPTD)
14 TPTD Peak Polarity 4 0, RO Polarity of the Fourth peak discovered by the TDR mechanism on Transmit Channel (TPTD)
13 TPTD Peak Polarity 3 0, RO Polarity of the Third peak discovered by the TDR mechanism on Transmit Channel (TPTD)
12 TPTD Peak Polarity 2 0, RO Polarity of the Second peak discovered by the TDR mechanism on Transmit Channel (TPTD)
11 TPTD Peak Polarity 1 0, RO Polarity of the First peak discovered by the TDR mechanism on Transmit Channel (TPTD)
10 TPRD Peak Polarity 5 0, RO Polarity of the Fifth peak discovered by the TDR mechanism on Receive Channel (TPRD)
9 TPRD Peak Polarity 4 0, RO Polarity of the Fourth peak discovered by the TDR mechanism on Receive Channel (TPRD)
8 TPRD Peak Polarity 3 0, RO Polarity of the Third peak discovered by the TDR mechanism on Receive Channel (TPRD)
7 TPRD Peak Polarity 2 0, RO Polarity of the Second peak discovered by the TDR mechanism on Receive Channel (TPRD)
6 TPRD Peak Polarity 1 0, RO Polarity of the First peak discovered by the TDR mechanism on Receive Channel (TPRD)
5 Cross Detect on TPTD 0, RO Cross Reflection were detected on TPTD. Indicate on Short between TPTD and TPRD
4 Cross Detect on TPRD 0, RO Cross Reflection were detected on TPRD. Indicate on Short between TPTD and TPRD
3 Above 5 TPTD Peaks 0, RO More than 5 reflections were detected on TPTD
2 Above 5 TPRD Peaks 0, RO More than 5 reflections were detected on TPRD
1:0 RESERVED 00, RO RESERVED: Writes ignored, read as 0

8.10.14 ALCD Control and Results 2 (ALCDRR2)

Table 8-55 ALCD Control and Results 2 (ALCDRR2), address 0x0215

BIT BIT NAME DEFAULT DESCRIPTION
15:4 RESERVED RO
3:0 alcd_out2 <0011>, RW Control word to analog PGA

8.10.15 ALCD Control and Results 3 (ALCDRR3)

Table 8-56 ALCD Control and Results 3 (ALCDRR3), address 0x021D

BIT BIT NAME DEFAULT DESCRIPTION
15:12 RESERVED 0000, RO RESERVED
11:0 FAGC Accumulator 0110 0000 0000, RW FAGC Accumulator: