SGLS307Q July   2006  – August 2024 TLK2711-SP

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 TTL Input Electrical Characteristics
    6. 5.6 Transmitter/Receiver Electrical Characteristics
    7. 5.7 Reference Clock (TXCLK) Timing Requirements
    8. 5.8 TTL Output Switching Characteristics
    9. 5.9 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1  Transmit Interface
      2. 6.3.2  Transmit Data Bus
      3. 6.3.3  Data Transmission Latency
      4. 6.3.4  8-Bit/10-Bit Encoder
      5. 6.3.5  Pseudo-Random Bit Stream (PRBS) Generator
      6. 6.3.6  Parallel to Serial
      7. 6.3.7  High-Speed Data Output
      8. 6.3.8  Receive Interface
      9. 6.3.9  Receive Data Bus
      10. 6.3.10 Data Reception Latency
      11. 6.3.11 Serial to Parallel
      12. 6.3.12 Comma Detect and 8-Bit/10-Bit Decoding
      13. 6.3.13 LOS Detection
      14. 6.3.14 PRBS Verification
      15. 6.3.15 Reference Clock Input
      16. 6.3.16 Operating Frequency Range
      17. 6.3.17 Testability
      18. 6.3.18 Loopback Testing
      19. 6.3.19 BIST
      20. 6.3.20 Power-On Reset
    4. 6.4 Device Functional Modes
      1. 6.4.1 Power-Down Mode
      2. 6.4.2 High-Speed I/O Directly-Coupled Mode
      3. 6.4.3 High-Speed I/O AC-Coupled Mode
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Application
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
      3. 7.2.3 Application Curves
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 Receiving Notification of Documentation Updates
    2. 8.2 Support Resources
    3. 8.3 Trademarks
    4. 8.4 Electrostatic Discharge Caution
    5. 8.5 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.3.11 Serial to Parallel

Serial data is received on the RXP and RXN pins. The interpolator and clock recovery circuit locks to the data stream if the clock to be recovered is within 200PPM of the internally generated bit rate clock. The recovered clock is used to retime the input data stream. The serial data is then clocked into the serial-to-parallel shift registers. The 10-bit-wide parallel data is then multiplexed and fed into two separate 8-bit/10-bit decoders, where the data is then synchronized to the incoming data stream word boundary by detection of the comma 8-bit/10-bit synchronization pattern.