SGLS307Q July   2006  – August 2024 TLK2711-SP

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 TTL Input Electrical Characteristics
    6. 5.6 Transmitter/Receiver Electrical Characteristics
    7. 5.7 Reference Clock (TXCLK) Timing Requirements
    8. 5.8 TTL Output Switching Characteristics
    9. 5.9 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1  Transmit Interface
      2. 6.3.2  Transmit Data Bus
      3. 6.3.3  Data Transmission Latency
      4. 6.3.4  8-Bit/10-Bit Encoder
      5. 6.3.5  Pseudo-Random Bit Stream (PRBS) Generator
      6. 6.3.6  Parallel to Serial
      7. 6.3.7  High-Speed Data Output
      8. 6.3.8  Receive Interface
      9. 6.3.9  Receive Data Bus
      10. 6.3.10 Data Reception Latency
      11. 6.3.11 Serial to Parallel
      12. 6.3.12 Comma Detect and 8-Bit/10-Bit Decoding
      13. 6.3.13 LOS Detection
      14. 6.3.14 PRBS Verification
      15. 6.3.15 Reference Clock Input
      16. 6.3.16 Operating Frequency Range
      17. 6.3.17 Testability
      18. 6.3.18 Loopback Testing
      19. 6.3.19 BIST
      20. 6.3.20 Power-On Reset
    4. 6.4 Device Functional Modes
      1. 6.4.1 Power-Down Mode
      2. 6.4.2 High-Speed I/O Directly-Coupled Mode
      3. 6.4.3 High-Speed I/O AC-Coupled Mode
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Application
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
      3. 7.2.3 Application Curves
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 Receiving Notification of Documentation Updates
    2. 8.2 Support Resources
    3. 8.3 Trademarks
    4. 8.4 Electrostatic Discharge Caution
    5. 8.5 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.3.12 Comma Detect and 8-Bit/10-Bit Decoding

The TLK2711-SP has two parallel 8-bit/10-bit decode circuits. Each 8-bit/10-bit decoder converts 10-bit encoded data (half of the 20-bit received word) back into 8 bits. The comma-detect circuit is designed to provide for byte synchronization to an 8-bit/10-bit transmission code. When parallel data is clocked into a parallel-to-serial converter, the byte boundary that was associated with the parallel data is now lost in the serialization of the data. When the serial data is received and converted to parallel format again, a method is needed to recognize the byte boundary. Typically, this is accomplished through the use of a synchronization pattern. This is typically a unique pattern of 1s and 0s that either cannot occur as part of valid data or is a pattern that repeats at defined intervals. The 8-bit/10-bit encoding contains a character called the comma (b0011111 or b1100000), which is used by the comma-detect circuit on the TLK2711-SP to align the received serial data back to its original byte boundary. The decoder detects the comma, generating a synchronization signal aligning the data to their 10-bit boundaries for decoding; the comma is mapped into the LSB. The decoder then converts the data back into 8-bit data. The output from the two decoders is latched into the 16-bit register synchronized to the recovered parallel data clock (RXCLK) and output valid on the rising edge of the RXCLK.

Note:

The TLK2711-SP only achieves byte alignment on the 0011111 comma.

Decoding provides two additional status signals, RKLSB and RKMSB. When RKLSB is asserted, an 8-bit/10-bit K code is received and the specific K code is presented on the data bits RXD0 to RXD7; otherwise, an 8-bit/10-bit D code is received. When RKMSB is asserted, an 8-bit/10-bit K code is received and the specific K-code is presented on data bits RXD8 to RXD15; otherwise, an 8-bit/10-bit D code is received (see Table 6-3). The valid K codes the TLK2711-SP; decodes are provided in Table 6-4. An error detected on either byte, including K codes not in Table 6-4, causes that byte only to indicate a K0.0 code on the RKxSB and associated data pins, where K0.0 is known to be an invalid 8-bit/10-bit code. A loss of input signal causes a K31.7 code to be presented on both bytes, where K31.7 is also known to be an invalid 8-bit/10-bit code.

Table 6-3 Receive Status Signals
RKLSBRKMSBDECODED 20-BIT OUTPUT
00Valid data on RXD0 to RXD7Valid data RXD8 to RXD15
01Valid data on RXD0 to RXD7K code on RXD8 to RXD15
10K code on RXD0 to RXD7Valid data on RXD8 to RXD15
11K code on RXD0 to RXD7K code on RXD8 to RXD15
Table 6-4 Valid K Characters
K CHARACTERRECEIVE DATA BUS
RXD7:RXD0 OR RXD15:RXD8
K28.0000 11100
K28.1(1)001 11100
K28.2010 11100
K28.3011 11100
K28.4100 11100
K28.5(1)101 11100
K28.6110 11100
K28.7(1)111 11100
K23.7111 10111
K27.7111 11011
K29.7111 11101
K30.7111 11110
(1) Should only be present on RXD0 to RXD7 when in running disparity < 0.