SNOSDJ3 May   2024 TLV1812-EP

ADVANCE INFORMATION  

  1.   1
  2. 1Features
  3. 2Applications
  4. 3Description
  5.   Pin Configuration and Functions
  6. 4Specifications
    1. 4.1 Absolute Maximum Ratings
    2. 4.2 ESD Ratings
    3. 4.3 Thermal Information - EP
    4. 4.4 Recommended Operating Conditions
    5. 4.5 Electrical Characteristics
    6. 4.6 Switching Characteristics
    7. 4.7 Typical Characteristics
  7. 5Detailed Description
    1. 5.1 Overview
    2. 5.2 Functional Block Diagrams
    3. 5.3 Feature Description
    4. 5.4 Device Functional Modes
      1. 5.4.1 Inputs
        1. 5.4.1.1 TLV18x2-EP Rail-to-Rail Input
        2. 5.4.1.2 ESD Protection
        3. 5.4.1.3 Unused Inputs
      2. 5.4.2 Outputs
        1. 5.4.2.1 TLV1812-EP Push-Pull Output
        2. 5.4.2.2 TLV1822-EP Open-Drain Output
      3. 5.4.3 Power-On Reset (POR)
      4. 5.4.4 Hysteresis
  8. 6Application and Implementation
    1. 6.1 Application Information
      1. 6.1.1 Basic Comparator Definitions
        1. 6.1.1.1 Operation
        2. 6.1.1.2 Propagation Delay
        3. 6.1.1.3 Overdrive Voltage
      2. 6.1.2 Hysteresis
        1. 6.1.2.1 Inverting Comparator With Hysteresis
        2. 6.1.2.2 Non-Inverting Comparator With Hysteresis
        3. 6.1.2.3 Inverting and Non-Inverting Hysteresis using Open-Drain Output
    2. 6.2 Typical Applications
      1. 6.2.1 Window Comparator
        1. 6.2.1.1 Design Requirements
        2. 6.2.1.2 Detailed Design Procedure
        3. 6.2.1.3 Application Curve
      2. 6.2.2 Square-Wave Oscillator
        1. 6.2.2.1 Design Requirements
        2. 6.2.2.2 Detailed Design Procedure
        3. 6.2.2.3 Application Curve
      3. 6.2.3 Adjustable Pulse Width Generator
      4. 6.2.4 Time Delay Generator
      5. 6.2.5 Logic Level Shifter
      6. 6.2.6 One-Shot Multivibrator
      7. 6.2.7 Bi-Stable Multivibrator
      8. 6.2.8 Zero Crossing Detector
      9. 6.2.9 Pulse Slicer
    3. 6.3 Power Supply Recommendations
    4. 6.4 Layout
      1. 6.4.1 Layout Guidelines
      2. 6.4.2 Layout Example
  9. 7Device and Documentation Support
    1. 7.1 Documentation Support
      1. 7.1.1 Related Documentation
    2. 7.2 Receiving Notification of Documentation Updates
    3. 7.3 Support Resources
    4. 7.4 Trademarks
    5. 7.5 Electrostatic Discharge Caution
    6. 7.6 Glossary
  10. 8Revision History
  11. 9Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5.4.2.2 TLV1822-EP Open-Drain Output

The TLV1822-EP features an open-drain (also commonly called open collector) sinking-only output stage enabling the output logic levels to be pulled up to an external voltage from 0V up to 40V, independent of the comparator supply voltage (V+). The open-drain output allows logical OR'ing of multiple open drain outputs and logic level translation. TI recommends setting the pull-up resistor current to between 100uA and 1mA. Lower value pull-up resistor values will help increase the rising edge rise-time, but at the expense of increasing VOL and higher power dissipation. The rise-time is dependent on the time constant of the total pull-up resistance and total load capacitance. Large value pull-up resistors (>1MΩ) will create an exponential rising edge due to the output RC time constant and increase the rise-time.

Directly shorting the output to V+ can result in thermal runaway and eventual device destruction at high (>12V) pull-up voltages. If output shorts are possible, a series current limiting resistor is recommended to limit the power dissipation.

Unused open drain outputs may be left floating, or may be tied to the V- pin if floating pins are not desired.