SNOSDJ3 May   2024 TLV1812-EP

ADVANCE INFORMATION  

  1.   1
  2. 1Features
  3. 2Applications
  4. 3Description
  5.   Pin Configuration and Functions
  6. 4Specifications
    1. 4.1 Absolute Maximum Ratings
    2. 4.2 ESD Ratings
    3. 4.3 Thermal Information - EP
    4. 4.4 Recommended Operating Conditions
    5. 4.5 Electrical Characteristics
    6. 4.6 Switching Characteristics
    7. 4.7 Typical Characteristics
  7. 5Detailed Description
    1. 5.1 Overview
    2. 5.2 Functional Block Diagrams
    3. 5.3 Feature Description
    4. 5.4 Device Functional Modes
      1. 5.4.1 Inputs
        1. 5.4.1.1 TLV18x2-EP Rail-to-Rail Input
        2. 5.4.1.2 ESD Protection
        3. 5.4.1.3 Unused Inputs
      2. 5.4.2 Outputs
        1. 5.4.2.1 TLV1812-EP Push-Pull Output
        2. 5.4.2.2 TLV1822-EP Open-Drain Output
      3. 5.4.3 Power-On Reset (POR)
      4. 5.4.4 Hysteresis
  8. 6Application and Implementation
    1. 6.1 Application Information
      1. 6.1.1 Basic Comparator Definitions
        1. 6.1.1.1 Operation
        2. 6.1.1.2 Propagation Delay
        3. 6.1.1.3 Overdrive Voltage
      2. 6.1.2 Hysteresis
        1. 6.1.2.1 Inverting Comparator With Hysteresis
        2. 6.1.2.2 Non-Inverting Comparator With Hysteresis
        3. 6.1.2.3 Inverting and Non-Inverting Hysteresis using Open-Drain Output
    2. 6.2 Typical Applications
      1. 6.2.1 Window Comparator
        1. 6.2.1.1 Design Requirements
        2. 6.2.1.2 Detailed Design Procedure
        3. 6.2.1.3 Application Curve
      2. 6.2.2 Square-Wave Oscillator
        1. 6.2.2.1 Design Requirements
        2. 6.2.2.2 Detailed Design Procedure
        3. 6.2.2.3 Application Curve
      3. 6.2.3 Adjustable Pulse Width Generator
      4. 6.2.4 Time Delay Generator
      5. 6.2.5 Logic Level Shifter
      6. 6.2.6 One-Shot Multivibrator
      7. 6.2.7 Bi-Stable Multivibrator
      8. 6.2.8 Zero Crossing Detector
      9. 6.2.9 Pulse Slicer
    3. 6.3 Power Supply Recommendations
    4. 6.4 Layout
      1. 6.4.1 Layout Guidelines
      2. 6.4.2 Layout Example
  9. 7Device and Documentation Support
    1. 7.1 Documentation Support
      1. 7.1.1 Related Documentation
    2. 7.2 Receiving Notification of Documentation Updates
    3. 7.3 Support Resources
    4. 7.4 Trademarks
    5. 7.5 Electrostatic Discharge Caution
    6. 7.6 Glossary
  10. 8Revision History
  11. 9Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

4.3 Thermal Information - EP

THERMAL METRIC(1) TLV1812-EP UNIT
DDF (SOT-23)
8 PINS
RθJA Junction-to-ambient thermal resistance 170.4 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 90.3 °C/W
RθJB Junction-to-board thermal resistance 88.1 °C/W
ψJT Junction-to-top characterization parameter 7.5 °C/W
ψJB Junction-to-board characterization parameter 87.6 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance – °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics report.