SNOSDG6 September   2024 TLV1831-Q1

ADVANCE INFORMATION  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
    1.     Pin Configuration: TLV1831-Q1 and TLV1841-Q1
    2.     Pin Configurations: TLV1832-Q1 and TLV1842-Q1
    3.     Pin Configuration and Functions: TLV1834-Q1 and TLV1844-Q1
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Thermal Information
    4. 5.4 Recommended Operating Conditions
    5. 5.5 Electrical Characteristics
    6. 5.6 Switching Characteristics
    7. 5.7 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagrams
    3. 6.3 Feature Description
    4. 6.4 Device Functional Modes
      1. 6.4.1 Inputs
        1. 6.4.1.1 Rail-to-Rail Input
        2. 6.4.1.2 Unused Inputs
      2. 6.4.2 Outputs
        1. 6.4.2.1 TLV183x-Q1 Push-Pull Output
        2. 6.4.2.2 TLV184x-Q1 Open-Drain Output
      3. 6.4.3 ESD Protection
        1. 6.4.3.1 Inputs
        2. 6.4.3.2 Outputs
      4. 6.4.4 Power-On Reset (POR)
  8. 7 Application and Implementation
    1. 7.1 Application Information
      1. 7.1.1 Basic Comparator Definitions
        1. 7.1.1.1 Operation
        2. 7.1.1.2 Propagation Delay
        3. 7.1.1.3 Overdrive Voltage
      2. 7.1.2 Hysteresis
        1. 7.1.2.1 Inverting Comparator With Hysteresis
        2. 7.1.2.2 Non-Inverting Comparator With Hysteresis
        3. 7.1.2.3 Inverting and Non-Inverting Hysteresis using Open-Drain Output
    2. 7.2 Typical Applications
      1. 7.2.1 Window Comparator
        1. 7.2.1.1 Design Requirements
        2. 7.2.1.2 Detailed Design Procedure
        3. 7.2.1.3 Application Curve
      2. 7.2.2 Square Wave Oscillator
        1. 7.2.2.1 Design Requirements
        2. 7.2.2.2 Detailed Design Procedure
        3. 7.2.2.3 Application Performance Plots
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 Documentation Support
      1. 8.1.1 Related Documentation
    2. 8.2 Receiving Notification of Documentation Updates
    3. 8.3 Support Resources
    4. 8.4 Trademarks
    5. 8.5 Electrostatic Discharge Caution
    6. 8.6 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5.3 Thermal Information

THERMAL METRIC(1) TLV18x2 UNIT
PW
(TSSOP)		 DSG
(WSON)		 DGK
(VSSOP)
8 PINS 8 PINS 8 PINS
RqJA Junction-to-ambient thermal resistance 157.6 - - °C/W
RqJC(top) Junction-to-case (top) thermal resistance 65.7 - - °C/W
RqJB Junction-to-board thermal resistance 96.5 - - °C/W
yJT Junction-to-top characterization parameter 8.1 - - °C/W
yJB Junction-to-board characterization parameter 95.2 - - °C/W
RqJC(bot) Junction-to-case (bottom) thermal resistance - - - °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics report.