SNOSDF2 august   2023 TLV1851-Q1 , TLV1861-Q1

PRODMIX  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Revision History
  6. 5 Pin Configuration and Functions
    1.     Pin Configuration: TLV1851-Q1 and TLV1861-Q1
    2.     Pin Configurations: TLV1852-Q1 and TLV1862-Q1
    3.     Pin Configurations: TLV1854-Q1 and TLV1864-Q1
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Thermal Information
    4. 6.4 Recommended Operating Conditions
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Characteristics
    7. 6.7 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagrams
    3. 7.3 Feature Description
    4. 7.4 Device Functional Modes
      1. 7.4.1 Inputs
        1. 7.4.1.1 Operating Common-Mode Ranges
        2. 7.4.1.2 Fail-Safe Inputs
        3. 7.4.1.3 Unused Inputs
      2. 7.4.2 Internal Hysteresis
      3. 7.4.3 Outputs
        1. 7.4.3.1 TLV185x-Q1 Push-Pull Output
        2. 7.4.3.2 TLV186x-Q1 Open-Drain Output
      4. 7.4.4 ESD Protection
        1. 7.4.4.1 Inputs
        2. 7.4.4.2 Outputs
      5. 7.4.5 Power-On Reset (POR)
      6. 7.4.6 Reverse Battery Protection
  9. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Basic Comparator Definitions
        1. 8.1.1.1 Operation
        2. 8.1.1.2 Propagation Delay
        3. 8.1.1.3 Overdrive Voltage
      2. 8.1.2 Hysteresis
        1. 8.1.2.1 Inverting Comparator With Hysteresis
        2. 8.1.2.2 Non-Inverting Comparator With Hysteresis
        3. 8.1.2.3 Inverting and Non-Inverting Hysteresis using Open-Drain Output
    2. 8.2 Typical Applications
      1. 8.2.1 Window Comparator
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
        3. 8.2.1.3 Application Curve
      2. 8.2.2 Undervoltage Detection
      3. 8.2.3 Reverse Battery and Overvoltage Protection Scheme
    3. 8.3 Power Supply Recommendations
  10. 9 Layout
    1. 9.1 Layout Guidelines
    2. 9.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Related Documentation
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 Support Resources
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 Glossary
  12. 11Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.3 Thermal Information

THERMAL METRIC(1) TLV185x/6x UNIT
DBV
(SOT-23)		 D
(SOIC)		 DGK
(VSSOP)		 PW
(TSSOP)		 D
(SOIC)
5 Pins 8 Pins 8 Pins 14 Pins 14 Pins
RqJA Junction-to-ambient thermal resistance 168.1 121.6 163.1 °C/W
RqJC(top) Junction-to-case (top) thermal resistance 68.1 64.6 55.5 °C/W
RqJB Junction-to-board thermal resistance 37.4 65.1 84.7 °C/W
yJT Junction-to-top characterization parameter 11.4 18.1 5.7 °C/W
yJB Junction-to-board characterization parameter 37.1 64.3 83.1 °C/W
RqJC(bot) Junction-to-case (bottom) thermal resistance °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.