The TLV187x has a unique "floating" output stage where the input and output have separate power supplies to allow defining the output levels without external level shifting. This allows directly sensing bipolar input signals using a split supply, and ground-referenced, low-voltage logic output designed for directly driving processors, ASICs or gate drivers.

The VCCI and VEEI pins supply the power to the input stage and comparator core. The VCCO and VEEO pins provide the power for the output stage and set the output swing.

The VCCO and VEEO pins are bounded by the VEEI and VCCI pins. Please see the Absolute Maximum Ratings and Recommended Operating Conditions tables for the specifications. Below is a summary of the limits.

Figure 6-2 Graphical View of Supply Limits

VCCI is the positive supply for the input stage and sets the positive input voltage range (Positive VCM). VCCI must be a minimum of 2.7V and up to a maximum of 40V above VEEI to establish the total operating voltage (V_S).

VCCO is the positive supply for the output stage, and sets the output high voltage level (VOH). VCCO must be at least 2.7V above VEEO and up to a maximum of VCCI.

VEEO is the negative supply for the output stage, and sets the output low voltage level (VOL). The VEEO pin must be equal to, or greater than the VEEI pin with up to a maximum +18V difference between the VEEI and VEEO pins.

VEEI is the negative supply for the input stage, and sets the negative input voltage range (negative VCM). The VEEI pin is the most negative "substrate" supply of the device. Therefore the VEEI pin must be at the most negative circuit potential. There must never be any more than 40V across the entire device with any combination of supply pins.

For example, an application where the input stage is VCCI = +15V, VEEI = –15V, and the output stage is using a single supply with VCCO = +3.3V and VEEO = GND is acceptable.

However, an application where VCCI = +5V, VEEI = GND, and the output stage using a split supply with VCCO = +12V and VEEO =-12V is NOT possible as that violates VEEO >= VEEI (VEEI is not the lowest negative potential) and VCCI < VCCO. If VCCI is instead connected to the +12V supply, and the VEEI is connected the -12V supply, that is acceptable.

Conversely, a negative input voltage application where VCCI = GND, VEEI = -12V, and the output stage using a single supply with VCCO = +3V and VEEO = GND is NOT possible as that violates VCCO >= VCCI (VEEO is greater than VCCI). In this case, instead tie VCCI to the +3V output supply and that is acceptable (VCCI = VCCO).

Single supply applications are also possible, with both VEEO and VEEI at GND, as long as VCCO is less than or equal to VCCI (VCCO <= VCCI). So VCCO = +3V and VCCI = +12V is acceptable, but VCCO = +12V and VCCI = +3V is NOT possible (instead, tie VCCI to the +12V to make acceptable).

Also possible is to have the output swing between two positive voltage values, such as +2V and +5V, (i.e., VEEO= +2V, VCCO = +5V) as long as the above conditions are followed (VCCI >= +5V and VEEO > VEEI) and there is a minimum of +2.7V between VEEO and VCCO.